US3649843A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mos bipolar push-pull output buffer
Assignee: Texas Instruments Inc
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Filing: 1969-06-26
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Granted: 1972-03-14
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Expires: 1989-06-26
Abstract
Abstract An output buffer for an MOS integrated logic circuit which utilizes an output stage comprised of a bipolar transistor and an MOS transistor connected in push-pull configuration is described. The output stage is operated by an MOS control circuit which utilizes an inverter stage with an improved capacitive bootstrap switching network to reduce the magnitude of the gate supply voltage required for positive switching. The circuit is characterized by very low input capacitance, and very low output impedance and thus high capacitive drive capability. A unique connection to ground internally of the integrated circuit is also described which comprises a diffusion made at the same time as the emitter diffusion of the bipolar transistor to provide ohmic contact between an overlying conductor and the substrate which then provides the return path to ground.
Inventors
- 👤 Donald J Redwine
- 👤 Earl M Worstell Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:14
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/347; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
94 words
An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the output of said buffer is taken from the emitter of said bipolar transistor.
Claim 2
Dependent Claim
94 words
An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the output of said buffer is taken from the emitter of said bipolar transistor.
Claim 3
Dependent Claim
168 words
The circuit of claim 1 wherein the control means comprises second, third, fourth and fifth MOS transistors, the channel of the second MOS transistor connecting the base of the bipolar transistor to the collector and the gate being connected to the logic input, the gate of the third field effect transistor being connected to the logic input, the channels of the third and fourth transistors being connected in series between the source supply voltage and the gate supply voltage with the common source-drain point being connected to the gate of the output transistor, the channel of the fifth MOS transistor interconnecting the gate of the fourth MOS transistor and the gate supply voltage, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the fourth MOS transistor to the common source-drain point of the third and fourth MOS transistors, the saturation impedance of the third MOS transistor being substantially less than that of the fourth MOS traNsistor.
Claim 4
Dependent Claim
46 words
The circuit of claim 2 further characterized by a sixth MOS transistor the channel of which is connected in parallel with the channel of the fourth MOS transistor, the saturation impedance of the sixth MOS transistor being substantially greater than that of the fourth MOS transistor.
Claim 5
Dependent Claim
47 words
The circuit of claim 3 further characterized by a seventh MOS transistor connecting the base of the bipolar transistor to the drain supply voltage of the output transistor, the gate of the seventh MOS transistor being connected to the common source-drain of the third and fourth transistors.
Claim 6
Dependent Claim
156 words
The control circuit for switching a first MOS transistor ''''on'''' and ''''off'''' in response to a logic control signal comprising second, third, fourth and fifth MOS transistors, the channels of the second and third MOS transistors being connected in series between a source supply voltage and a gate supply voltage with the common drain-source point being connected to the gate of the first MOS transistor, the gate of the third MOS transistor being connected by the channel of the fourth MOS transistor to the gate supply voltage, the gate of the fourth MOS transistor being connected to the gate supply voltage, the channel of the fifth MOS transistor being connected in parallel with the channel of the third MOS transistor, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the third MOS transistor to the common drain-source of the second and third MOS transistors.
Claim 7
Dependent Claim
156 words
The control circuit for switching a first MOS transistor ''''on'''' and ''''off'''' in response to a logic control signal comprising second, third, fourth and fifth MOS transistors, the channels of the second and third MOS transistors being connected in series between a source supply voltage and a gate supply voltage with the common drain-source point being connected to the gate of the first MOS transistor, the gate of the third MOS transistor being connected by the channel of the fourth MOS transistor to the gate supply voltage, the gate of the fourth MOS transistor being connected to the gate supply voltage, the channel of the fifth MOS transistor being connected in parallel with the channel of the third MOS transistor, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the third MOS transistor to the common drain-source of the second and third MOS transistors.
Claim 8
Dependent Claim
136 words
An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the control means comprises an MOS inverter stage for receiving the logic signal, the output of which is connected to the gate of the output transistor, and a third field effect transistor connecting the base of the bipolar output transistor to the collector, the gate of the third transistor being connected to receive the logic signal.
Claim 9
Dependent Claim
136 words
An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the control means comprises an MOS inverter stage for receiving the logic signal, the output of which is connected to the gate of the output transistor, and a third field effect transistor connecting the base of the bipolar output transistor to the collector, the gate of the third transistor being connected to receive the logic signal.
Claim 10
Dependent Claim
91 words
In an integrated semiconductor circuit, the combination comprising a substrate of one conductivity type, a source region and a drain region of the other conductivity type, means coupling the source region to the drain region to form a first field effect transistor, a base region of said other conductivity type having disposed therein an emitter region of said one conductivity type to form a bipolar transistor, means coupling the emitter region to the source region to form an emitter-source junction, and wherein the emitter-source junction is the output of the circuit.
Claim 11
Dependent Claim
91 words
In an integrated semiconductor circuit, the combination comprising a substrate of one conductivity type, a source region and a drain region of the other conductivity type, means coupling the source region to the drain region to form a first field effect transistor, a base region of said other conductivity type having disposed therein an emitter region of said one conductivity type to form a bipolar transistor, means coupling the emitter region to the source region to form an emitter-source junction, and wherein the emitter-source junction is the output of the circuit.
Claim 12
Dependent Claim
39 words
The combination of claim 7 further including means coupling the drain region to a first potential and means coupling the collector region to a second potential different from the first potential for providing operating potentials for said semiconductor circuit.
Claim 13
Dependent Claim
58 words
The combination of claim 7 further characterized by means forming a control circuit for turning the field effect channel ''''on'''' and the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect channel ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal.
Claim 14
Dependent Claim
37 words
The combination of claim 8 wherein the control circuit includes at least one diffusion of the one conductivity type directly contacting the substrate and a metal conductor in contact with said last mentioned at least one diffusion.
Claim 15
Dependent Claim
62 words
The circuit of claim 9 wherein the control means comprises an MOS inverter stAge for receiving the logic signal the output of which is connected to the gate of the output transistor, and a third field effect transistor connecting the base of the bipolar output transistor to the collector, the gate of the third transistor being connected to receive the logic signal.
Claim 16
Dependent Claim
146 words
The combination of claim 9 wherein the control circuit comprises second, third, fourth and fifth MOS transistors, the channels of the second and third MOS transistors being connected in series between a source supply voltage and a gate supply voltage with the common drain-source point being connected to the gate of the first MOS transistor, the gate of the third MOS transistor being connected by the channel of the fourth MOS transistor to the gate supply voltage, the gate of the fourth MOS transistor being connected to the gate supply voltage, the channel of the fifth MOS transistor being connected in parallel with the channel of the third MOS transistor, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the third MOS transistor to the common drain-source of the second and third MOS transistors.
References Cited (Backward Citations)
US3506851A
Cited
US3466511A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-14 | 1975-09-13 | 1976-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-14 | 1979-09-13 | 1980-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-14 | 1983-09-13 | 1984-03-14 | $7700.00 | Window Closed / Lapsed |