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US3602779A Expired / Lapsed US ⏱️ 0.0 years remaining

Epitaxial transistor with limited area buried layer and lifetimekillers

Assignee: US Philips Corp
•
Filing: 1969-06-26
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Granted: 1971-08-31
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Expires: 1989-06-26
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Abstract

Abstract A transistor of the planar type with epitaxial layer and lifetime killers is described. A buried layer for reducing collector resistance is located directly under a collector contact and only that part of the base region which directly surrounds the emitter region, leaving an adjacent part of the base region free of the buried layer. This allows lifetime killers when diffused in from the back to spread throughout the collector and base region without sacrificing the collector resistance.

Inventors

  • 👤 Claude Chapron

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 16:05
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085; Y10S148/145

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 231 words
A semiconductor device having a transistor, said transistor comprising a semiconductor substrate body having top and bottom major surfaces and an epitaxial layer on its top surface; said transistor further comprising a surface base region in the epitaxial layer and spaced from the substrate, a surface emitter region nested in the base region, and a collector region; said collector region comprising a part of the epitaxial layer completely surrounding the base region and extending to the epitaxial layer surface and of relatively high resistivity, a collector contact surface region of relatively low resistivity and laterally spaced from the base region, and a buried layer of relatively low resistivity and located at the epitaxial layer substrate interface and extending directly underneath the collector contact region and up to and underneath only that portion of the base region directly surrounding the emitter region such that a substantial part of the epitaxial layer extending underneath other lateral portions of the base region not directly surrounding the emitter region and the underlying epitaxial layer-substrate interface remain free of the buried layer; emitter, base, and collector connections to respectively the emitter, the base, and the collector contact regions at the epitaxial layer surface, and a carrier lifetime-reducing impurity in the substrate, the collector region and the base region, said carrier lifetime reducing impurity having been introduced into the transistor via the bottom surface of the substrate.
Claim 2
Dependent Claim 231 words
A semiconductor device having a transistor, said transistor comprising a semiconductor substrate body having top and bottom major surfaces and an epitaxial layer on its top surface; said transistor further comprising a surface base region in the epitaxial layer and spaced from the substrate, a surface emitter region nested in the base region, and a collector region; said collector region comprising a part of the epitaxial layer completely surrounding the base region and extending to the epitaxial layer surface and of relatively high resistivity, a collector contact surface region of relatively low resistivity and laterally spaced from the base region, and a buried layer of relatively low resistivity and located at the epitaxial layer substrate interface and extending directly underneath the collector contact region and up to and underneath only that portion of the base region directly surrounding the emitter region such that a substantial part of the epitaxial layer extending underneath other lateral portions of the base region not directly surrounding the emitter region and the underlying epitaxial layer-substrate interface remain free of the buried layer; emitter, base, and collector connections to respectively the emitter, the base, and the collector contact regions at the epitaxial layer surface, and a carrier lifetime-reducing impurity in the substrate, the collector region and the base region, said carrier lifetime reducing impurity having been introduced into the transistor via the bottom surface of the substrate.
Claim 3
Dependent Claim 82 words
A semiconductor device as claimed in claim 1 wherein plural spaced but electrically interconnected surface emitter regions are nested within the said base region near its circumference, plural spaced but electrically interconnected surface collector contact regions are provided within the epitaxial layer each near an emitter region, and the buried layer comprises plural parts each situated directly below a collector contact and extending up to and underneath the part of the base region directly surrounding the emitter region nearest said collector contact.
Claim 4
Dependent Claim 35 words
A semiconductor device as set forth in claim 2, wherein the impurity is gold and is diffused within the substrate, the collector region and the base region via the entire bottom surface of the substrate.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-08-30 1975-03-01 1975-08-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-08-30 1979-03-01 1979-08-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-08-30 1983-03-01 1983-08-31 $7700.00 Window Closed / Lapsed

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