BiMOS logical circuit

Claim 1

A BiMOS circuit comprising: a first transistor comprised of a PMOS transistor; a second transistor comprised of an NMOS transistor; a third transistor comprised of a bipolar transistor; a fourth transistor comprised of an NMOS transistor; and a fifth transistor comprised of an NMOS transistor; one end of said first transistor and one end of said second transistor being connected to each other at an intermediate node of said respective one ends of said first and second transistors, the gate of said first transistor and the gate of said second transistor being connected to an input terminal, a first power supply voltage being supplied to the other end of one of said first and second transistors, a control signal being delivered to the other end of the other transistor thereof; the base of said third transistor being connected to said intermediate node, a second power supply voltage being applied to one of the collector or the emitter of said third transistor, an output terminal being connected to the other thereof; respective one ends of said fourth and fifth transistors being connected to said output terminal, said first power supply voltage being applied to the respective other ends thereof, the gate of said fourth transistor being connected to said input terminal, a signal complementary to said control signal being delivered to the gate of said fifth transistor.