US4740718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-CMOS logic circuit
Assignee: Toshiba Corp
•
Filing: 1987-03-30
•
Granted: 1988-04-26
•
Expires: 2007-03-30
Abstract
Abstract A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
Inventors
- 👤 Masataka Matsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
215 words
A Bi-CMOS logic circuit comprising: a totem pole-type output buffer including a first NPN bipolar transistor having a collector coupled to a power supply potential, an emitter and a base, and a second NPN bipolar transistor having a collector coupled to the emitter of said first NPN bipolar transistor via a node, an emitter coupled to a ground potential, and a base, a potential at the node of said first and second NPN bipolar transistors being used as an output signal; a CMOS logic circuit having at least one input terminal for receiving an input signal, and an output terminal which is connected to the base of said first NPN bipolar transistor; and latch means including at least one pair of first and second N-type MOSFETs, said first N-type MOSFET having a gate coupled to the input terminal of said CMOS logic circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said second N-type MOSFET having a drain coupled to the input terminal of said CMOS logic circuit, a gate coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
Claim 2
Dependent Claim
215 words
A Bi-CMOS logic circuit comprising: a totem pole-type output buffer including a first NPN bipolar transistor having a collector coupled to a power supply potential, an emitter and a base, and a second NPN bipolar transistor having a collector coupled to the emitter of said first NPN bipolar transistor via a node, an emitter coupled to a ground potential, and a base, a potential at the node of said first and second NPN bipolar transistors being used as an output signal; a CMOS logic circuit having at least one input terminal for receiving an input signal, and an output terminal which is connected to the base of said first NPN bipolar transistor; and latch means including at least one pair of first and second N-type MOSFETs, said first N-type MOSFET having a gate coupled to the input terminal of said CMOS logic circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said second N-type MOSFET having a drain coupled to the input terminal of said CMOS logic circuit, a gate coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
Claim 3
Dependent Claim
33 words
A Bi-CMOS logic circuit according to claim 1, wherein said CMOS logic circuit includes a one-input CMOS inverter circuit having an output terminal connected to the base of said first NPN bipolar transistor.
Claim 4
Dependent Claim
40 words
A Bi-CMOS logic circuit according to claim 1, wherein said CMOS logic circuit includes a CMOS NOR circuit having first and second input terminals, and an output terminal which is connected to the base of said first NPN bipolar transistor.
Claim 5
Dependent Claim
168 words
A Bi-CMOS logic circuit according to claim 3, wherein said latch means include two pairs of N-type MOSFETs, one of those pairs consists of said first and second N-type MOSFETs, and the other pair consists of third and forth N-type MOSFETs, said first N-type MOSFET having the gate coupled to said first input terminal of said CMOS NOR circuit, said second N-type MOSFET having the drain coupled to said first input terminal of said CMOS NOR circuit, said third N-type MOSFET having a gate coupled to said second input terminal of said CMOS NOR circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said fourth N-type MOSFET having a drain coupled to said second input terminal of said CMOS NOR circuit, a gate coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
Claim 6
Dependent Claim
24 words
A Bi-CMOS logic circuit according to claim 1, wherein said first N-type MOSFET has a conductance greater than that of said second N-type MOSFET.
Claim 7
Dependent Claim
213 words
A Bi-CMOS logic circuit comprising: a totem pole-type output buffer including a first NPN bipolar transistor having a collector coupled to a power supply potential, an emitter and a base, and a second NPN bipolar transistor having a collector coupled to the emitter of said first NPN bipolar transistor via a node, an emitter coupled to a ground potential and a base, a potential at the node of said first and second NPN bipolar transistors being used as an output signal; a CMOS logic circuit having at least one input terminal for receiving an input signal, and an output terminal which is connected to the base of said first NPN bipolar transistor; and latch means including at least one pair of first and second N-type MOSFETs, said first N-type MOSFET having a gate coupled to the input terminal of said CMOS logic circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said second N-type MOSFET having a drain coupled to the input terminal of said CMOS logic circuit, a gate coupled to the output terminal of said CMOS logic circuit, and a source coupled to the base of said second NPN bipolar transistor.
Claim 8
Dependent Claim
213 words
A Bi-CMOS logic circuit comprising: a totem pole-type output buffer including a first NPN bipolar transistor having a collector coupled to a power supply potential, an emitter and a base, and a second NPN bipolar transistor having a collector coupled to the emitter of said first NPN bipolar transistor via a node, an emitter coupled to a ground potential and a base, a potential at the node of said first and second NPN bipolar transistors being used as an output signal; a CMOS logic circuit having at least one input terminal for receiving an input signal, and an output terminal which is connected to the base of said first NPN bipolar transistor; and latch means including at least one pair of first and second N-type MOSFETs, said first N-type MOSFET having a gate coupled to the input terminal of said CMOS logic circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said second N-type MOSFET having a drain coupled to the input terminal of said CMOS logic circuit, a gate coupled to the output terminal of said CMOS logic circuit, and a source coupled to the base of said second NPN bipolar transistor.
Claim 9
Dependent Claim
33 words
A Bi-CMOS logic circuit according to claim 6, wherein said CMOS logic circuit includes a one-input CMOS inverter circuit having an output terminal connected to the base of said first NPN bipolar transistor.
Claim 10
Dependent Claim
40 words
A Bi-CMOS logic circuit according to claim 6, wherein said CMOS logic circuit includes a CMOS NOR circuit having first and second input terminals, and an output terminal which is connected to the base of said first NPN bipolar transistor.
Claim 11
Dependent Claim
166 words
A Bi-CMOS logic circuit according to claim 8, wherein said latch means include two pairs of N-type MOSFETs, one of those pairs consists of said first and second N-type MOSFETs, and the other pair consists of third and fourth N-type MOSFETs, said first N-type MOSFET having the gate coupled to said first input terminal of said CMOS NOR circuit, said second N-type MOSFET having the drain coupled to said first input terminal of said CMOS NOR circuit, said third N-type MOSFET having a gate coupled to said second input terminal of said CMOS NOR circuit, a drain coupled to the node of said first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor, and said fourth N-type MOSFET having a drain coupled to said second input terminal of said CMOS NOR circuit, a gate coupled to the output terminal of said CMOS NOR circuit, and a source coupled to the base of said second NPN bipolar transistor.
Claim 12
Dependent Claim
24 words
A Bi-CMOS logic circuit according to claim 6, wherein said first N-type MOSFET has a conductance greater than that of said second N-type MOSFET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |