US4616146A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BI-CMOS driver circuit
Assignee: NXP USA Inc
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Filing: 1984-09-04
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Granted: 1986-10-07
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Expires: 2004-09-04
Abstract
Abstract A BI-CMOS circuit is provided wherein an output terminal is coupled between an upper and lower NPN push-pull transistor. This provides high current drive capability along with no d.c. power dissipation. A P-channel device has a source and a drain connected to the collector and base, respectively, of the upper NPN transistor. An N-channel device has a source and drain connected to the base and collector, respectively, of the lower NPN transistor. The gates of the P-channel and N-channel devices are connected to an input terminal and provide a high impedance thereat. Additional N-channel devices are coupled between the bases of the upper and lower NPN transistors and a supply voltage terminal for improving the switching speed of the output signal.
Inventors
- 👤 Shi-Chuan Lee
- 👤 Douglas W. Schucker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
232 words
A gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in parallel between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in series between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a third plurality of MOS transistors, each having its drain-source current path coupled in series between said base of said first bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said base of said first bipolar transistor.
Claim 2
Dependent Claim
232 words
A gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in parallel between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in series between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a third plurality of MOS transistors, each having its drain-source current path coupled in series between said base of said first bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to one of said plurality of input terminals; and a first MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said base of said first bipolar transistor.
Claim 3
Dependent Claim
238 words
A gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in series between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in parallel between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a third plurality of MOS transistors, each having its drain-source current path coupled in parallel between said base of said first bipolar transistor and said second supply voltage terminal, each of said third plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said base of said first bipolar transistor.
Claim 4
Dependent Claim
238 words
A gate circuit comprising: a plurality of input terminals; an output terminal; a first bipolar transistor having its emitter-collector current path coupled between a first supply voltage terminal and said output terminal; a second bipolar transistor having its emitter-collector current path coupled between said output terminal and a second supply voltage terminal; a first plurality of MOS transistors, each having its drain-source current path coupled in series between said first supply voltage terminal and a base of said first bipolar transistor, each of said first plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a second plurality of MOS transistors, each having its drain-source current path coupled in parallel between said output terminal and a base of said second bipolar transistor, each of said second plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; a third plurality of MOS transistors, each having its drain-source current path coupled in parallel between said base of said first bipolar transistor and said second supply voltage terminal, each of said third plurality of MOS transistors having a control electrode coupled to one of said plurality of input terminals; and a MOS transistor having its drain-source current path coupled between said base of said second bipolar transistor and said second supply voltage terminal, and having a control electrode coupled to said base of said first bipolar transistor.
References Cited (Backward Citations)
EP0058958A2
Cited
EP0099100A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |