Complementary MOSFET logic circuit

Claim 2

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 42; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said complementary MOSFET circuit (23; 35; 45) and threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output characteristic of a TTL circuit.

Claim 3

A complementary MOSFET logic circuit according to claim 1, wherein an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) is adapted for an output voltage characteristic of a TTL circuit by setting the ratio of the channel widths of said P channel MOSFET and said N channel MOSFET and threshold voltages at proper values.

Claim 4

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is an inverter.

Claim 5

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is a NOR circuit.

Claim 6

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is a NAND circuit.

Claim 7

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is an inverter, and in said buffer circuit, one MOSFET (26) which receives at the gate an input signal applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 8

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is a NOR circuit, and in said buffer circuit, two or more MOSFETs (38, 39) connected in parallel which receive at the gates input signals applied to said complementary MOSF E T circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 9

A complementary MOSFET logic circuit according to claim 1, wherein said complementary MOSFET circuit is a NAND circuit, and in said buffer circuit, two or more series-connected MOSFETs (48, 49) which receive at the gates input signals to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 10

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one MOSFET connected in parallel with said bipolar transistor (25; 37; 47; 27) for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 11

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one MOSFET connected in parallel with said bipolar transistor (25; 37; 47; 27) for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 12

A complementary MOSFET logic circuit according to claim 9, wherein an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) is adapted for an output voltage characteristic of a TTL circuit by setting the ratio of the channel widths of said P channel MOSFET and said N channel MOSFET and threshold voltages at proper values.

Claim 13

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is an inverter.

Claim 14

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NOR circuit.

Claim 15

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NAND circuit.

Claim 16

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is an inverter, and in said buffer circuit, one MOSFET (26) which receives at the gate an input signal applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 17

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NOR circuit, and in said buffer circuit, two or more MOSFETs (38, 39) connected in parallel which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 18

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NAND circuit, and in said buffer circuit, two or more series-connected MOSFETs (48, 49) which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 19

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is an inverter, and one MOSFET (51) which receives at the gate an input signal applied to said complementary MOSFET circuit is connected in parallel with said bipolar transistor.

Claim 20

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NOR circuit, and two or more MOSFETs (52, 53) connected in series which receive at the gates input signals applied to said complementary MOSFET circuit are connected in parallel with said bipolar transistor.

Claim 21

A complementary MOSFET logic circuit according to claim 9, wherein said complementary MOSFET circuit is a NAND circuit, and two or more MOSFETs (54, 55) connected in parallel which receive at the gates input signals applied to said complementary MOSFET circuit are coupled with said bipolar transistor.

Claim 22

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one P channel MOSFET, which is inserted between said high potential applying point and the output terminal of said complementary MOSFET circuit (23; 35; 45) and receives at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), has a threshold voltage different from that of one P channel MOSFET in said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 23

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one P channel MOSFET, which is inserted between said high potential applying point and the output terminal of said complementary MOSFET circuit (23; 35; 45) and receives at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), has a threshold voltage different from that of one P channel MOSFET in said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 24

A complementry MOSFET logic circuit according to claim 20, wherein an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) is adapted for an output voltage characteristic of a TTL circuit by setting the ratio of the channel widths of said P channel MOSFET and said N channel MOSFET and threshold voltages at proper values.

Claim 25

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is an inverter.

Claim 26

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NOR circuit.

Claim 27

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NAND circuit.

Claim 28

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is an inverter, and in said buffer circuit, one MOSFET (26) which receives at the gate an input signal applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 29

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NOR circuit, and in said buffer circuit, two or more MOSFETs (38, 39) connected in parallel which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 30

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NAND circuit, and in said buffer circuit, two or more series-connected MOSFETs (48, 49) which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 31

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is an inverter, and one P channel MOSFET, which receives at the gate an input signal applied to said complementary MOSFET circuit and has a threshold voltage different from that of one P channel MOSFET (61; 66) in said complementary MOSFET circuit, is inserted between the output terminals of said high potential applying point and the output terminal of said complementary MOSFET circuit.

Claim 32

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NOR circuit, and two or more P channel MOSFETs (62, 63) connected in series, which receive at the gates input signals applied to said complementary MOSFET circuit, and have threshold voltages different from those of P channel MOSFETs in said complementary MOSFET circuit, are inserted between said high potential applying point and said complementary MOSFET circuit.

Claim 33

A complementary MOSFET logic circuit according to claim 20, wherein said complementary MOSFET circuit is a NAND circuit, and two or more P channel MOSFETs (64, 65) connected in parallel, which receive at the gates input signals applied to said complementary MOSFET circuit and have threshold voltages different from those of P channel MOS FETs in said complementary MOSFET circuit, are inserted between said high potential applying point and the output terminal of said complementary MOSFET circuit.

Claim 34

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said-complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one MOSFET, which is.connected in parallel with said bipolar transistor (25; 37; 47; 27) for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), is provided, and at least one P channel MOSFET, which is connected between said high potential and the output terminal of said complementary MOSFET circuit (23; 35; 45) for receiving at the gate an input signal applied to said complementary MOSFET circuit and has a threshold voltage different from that of a P channel MOSFET in said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 35

A complementary MOSFET logic circuit comprising a complementary MOSFET circuit (23; 35; 45) including at least one P channel MOSFET and one N channel MOSFET, and a buffer circuit in which a bipolar transistor (25; 37; 47; 27) for receiving at the base a signal appearing at the output terminal of said complementary MOSFET circuit (23; 35; 45) and at least one MOSFET for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45) are inserted in series between a high potential applying point and a low potential applying point, and an output signal corresponding to a logic output signal of said complementary MOSFET circuit (23; 35; 45) is produced at the output terminal of said buffer circuit, wherein a ratio of the channel sizes of a P channel MOSFET and an N channel MOSFET in said-complementary MOSFET circuit (23; 35; 45) and the threshold voltages of said MOSFETs are set at pregiven values so as to make an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) corresponding to an output voltage characteristic of a TTL circuit, and at least one MOSFET, which is.connected in parallel with said bipolar transistor (25; 37; 47; 27) for receiving at the gate an input signal applied to said complementary MOSFET circuit (23; 35; 45), is provided, and at least one P channel MOSFET, which is connected between said high potential and the output terminal of said complementary MOSFET circuit (23; 35; 45) for receiving at the gate an input signal applied to said complementary MOSFET circuit and has a threshold voltage different from that of a P channel MOSFET in said complementary MOSFET circuit (23; 35; 45), is further provided.

Claim 36

A complementary MOSFET logic circuit according to claim 31, wherein an input voltage characteristic of said complementary MOSFET circuit (23; 35; 45) is adapted for an output voltage characteristic of a TTL circuit by setting the ratio of the channel widths of said P channel MOSFET and said N channel MOSFET and threshold voltages at proper values.

Claim 37

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is an inverter.

Claim 38

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NOR circuit.

Claim 39

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NAND circuit.

Claim 40

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is an inverter, and in said buffer circuit, one MOSFET (26) which receives at the gate an input signal applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 41

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NOR circuit, and in said buffer circuit, two or more MOSFETs (38, 39) connected in parallel which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 42

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NAND circuit, and in said buffer circuit, two or more series-connected MOSFETs (48, 49) which receive at the gates input signals applied to said complementary MOSFET circuit, together with said bipolar transistor, are inserted in series between the high potential applying point and the low potential applying point.

Claim 43

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is an inverter, and in said buffer circuit, one MOSFET (51; 56) which receives at the gate an input signal applied to said complementary MOSFET is connected in parallel with said bipolar transistor.

Claim 44

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NOR circuit, and in said buffer circuit, two or more MOSFETs (52, 53) connected in series which receive at the gates input signals applied to said complementary MOSFET circuit are connected in parallel with said bipolar transistor.

Claim 45

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NAND circuit, and in said buffer circuit, two or more MOSFETs (54, 55) connected in parallel which receive at the gates input signals applied to said complementary MOSFET circuit are coupled with said bipolar transistor.

Claim 46

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is an inverter, and one P channel MOSFET (61; 66), which receive at the gate an input signal applied to said complementary MOSFET circuit and has a threshold voltage different from that of one P channel MOSFET in said complementary MOSFET circuit, is inserted between the output terminal of said high potential applying point and the output terminal of said complementary MOSFET circuit.

Claim 47

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NOR circuit, and two or more P channel MOSFETs (62, 63) connected in series, which receive input signals applied to said complementary MOSFET circuit, and have threshold voltages different from those of P channel MOSFETs in said complementary MOSFET circuit, are inserted between said high potential applying point and said complementary MOSFET circuit.

Claim 48

A complementary MOSFET logic circuit according to claim 31, wherein said complementary MOSFET circuit is a NAND circuit, and two or more P channel MOSFETs (64, 65) connected in parallel, which receive at the gates input signals applied to said complementary MOSFET circuit and have threshold voltages different from those of P channel MOSFETs in said complementary MOSFET circuit, are inserted between said high potential applying point and the output terminal of said complementary MOSFET circuit.