US6269451B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for adjusting data timing by delaying clock signal
Assignee: Round Rock Research LLC
•
Filing: 1998-02-27
•
Granted: 2001-07-31
•
Expires: 2018-02-27
Abstract
Abstract A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.
Inventors
- 👤 Patrick J. Mullarkey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:17
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F2205/00; G06F2205/10; G06F2205/104
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
195 words
A data delay circuit comprising: an external clock terminal adapted to receive an external clock signal having a first state and a second state; an adjustable time delay circuit having a plurality of control inputs each adapted to receive a respective control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, the adjustable time delay circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the time between when the external clock signal changes states and when the delayed clock signal changes states; and a data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the delayed clock signal changes from the first to the second state.
Claim 2
Dependent Claim
195 words
A data delay circuit comprising: an external clock terminal adapted to receive an external clock signal having a first state and a second state; an adjustable time delay circuit having a plurality of control inputs each adapted to receive a respective control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, the adjustable time delay circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the time between when the external clock signal changes states and when the delayed clock signal changes states; and a data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the delayed clock signal changes from the first to the second state.
Claim 3
Dependent Claim
21 words
The circuit of claim 1 wherein the control signals are generated by selectively coupling the control inputs to a reference voltage.
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein each of the control inputs is selectively coupled to a reference voltage using a respective fuse.
Claim 5
Dependent Claim
22 words
The circuit of claim 2 wherein each of the control inputs is selectively coupled to a reference voltage using a respective antifuse.
Claim 6
Dependent Claim
71 words
The circuit of claim 1 wherein the: plurality of passgates are arranged in columns, each column having a different number of passgates than any other column in the time delay circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective one of the delay elements, and the external clock signal coupled to and passing through each of the delay elements.
Claim 7
Dependent Claim
16 words
The circuit of claim 5 wherein one of the delay elements has a null delay value.
Claim 8
Dependent Claim
44 words
The circuit of claim 5 wherein each of the columns is coupled to the columns adjacent to it such that one-half of the total number of passgates in each column are coupled to one-half of the total number of passgates in each adjacent column.
Claim 9
Dependent Claim
50 words
The circuit of claim 5 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 10
Dependent Claim
56 words
The circuit of claim 5 wherein each control signals controls all of the passgates in a respective one of the columns, with one-half of the passgates in the respective column controlled to a passing state and the remainder of the passgates in the respective column controlled to a blocking state responsive to the respective control signal.
Claim 11
Dependent Claim
147 words
A clocked-data phase adjustment circuit comprising: a reference clock terminal adapted to receive a reference clock signal having a first state and a second state; a data terminal adapted to receive a data signal; and a phase shifting circuit adapted to receive a plurality of control signals, the reference clock signal, and the data signal each at respective inputs, the phase shifting circuit being adapted to adjust the time when the data signal is passed from the data input terminal to a data output terminal responsive to the phase of the reference clock signal, the phase of the reference clock signal being determined by the control signals, the phase shifting circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the reference clock signal.
Claim 12
Dependent Claim
147 words
A clocked-data phase adjustment circuit comprising: a reference clock terminal adapted to receive a reference clock signal having a first state and a second state; a data terminal adapted to receive a data signal; and a phase shifting circuit adapted to receive a plurality of control signals, the reference clock signal, and the data signal each at respective inputs, the phase shifting circuit being adapted to adjust the time when the data signal is passed from the data input terminal to a data output terminal responsive to the phase of the reference clock signal, the phase of the reference clock signal being determined by the control signals, the phase shifting circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the reference clock signal.
Claim 13
Dependent Claim
21 words
The circuit of claim 10 wherein the control signals are generated by selectively coupling the control inputs to a reference voltage.
Claim 14
Dependent Claim
22 words
The circuit of claim 11 wherein each of the control inputs is selectively coupled to a reference voltage using a respective fuse.
Claim 15
Dependent Claim
22 words
The circuit of claim 11 wherein each of the control inputs is selectively coupled to a reference voltage using a respective antifuse.
Claim 16
Dependent Claim
70 words
The circuit of claim 10 wherein the: passgates are arranged in columns, each column having a different number of passgates than any other column in the phase shifting circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective one of the delay elements, and the external clock signal being coupled to and passing through each of the delay elements.
Claim 17
Dependent Claim
16 words
The circuit of claim 14 wherein one of the delay elements has a null delay value.
Claim 18
Dependent Claim
44 words
The circuit of claim 14 wherein each of the columns is coupled to the columns adjacent to it such that one-half of the total number of passgates in each column are coupled to one-half of the total number of passgates in each adjacent column.
Claim 19
Dependent Claim
50 words
The circuit of claim 14 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 20
Dependent Claim
54 words
The circuit of claim 14 wherein each control signals controls all of the passgates in a respective one of the columns, with one-half of the passgates in the respective column in a passing state and the remainder of the passgates in the respective column in a blocking state responsive to the respective control signal.
Claim 21
Dependent Claim
246 words
In a synchronous memory circuit, a circuit to adjust output data timing comprising: an external clock terminal adapted to receive an external clock signal having a first state and a second state; a clock filtering circuit coupled to the external clock terminal, the clock filtering circuit adapted to modifying the external clock signal into a data clock signal; a data terminal adapted to receive a data signal; an adjustable time delay circuit having a plurality of control inputs each receiving a respective control signal, the time delay circuit adapted to receive the data clock signal at a clock input and passing a time adjusted data clock signal to an output terminal, the time between when the data clock signal changes states and when the time adjusted data clock signal changes states determined by the control signals received at the control inputs, the adjustable time delay circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the time adjusted data clock signal relative to the phase of the data clock signal; and a data passing circuit adapted to receive both the data signal and the time adjusted data clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the time adjusted data clock signal changes from the first to the second state.
Claim 22
Dependent Claim
246 words
In a synchronous memory circuit, a circuit to adjust output data timing comprising: an external clock terminal adapted to receive an external clock signal having a first state and a second state; a clock filtering circuit coupled to the external clock terminal, the clock filtering circuit adapted to modifying the external clock signal into a data clock signal; a data terminal adapted to receive a data signal; an adjustable time delay circuit having a plurality of control inputs each receiving a respective control signal, the time delay circuit adapted to receive the data clock signal at a clock input and passing a time adjusted data clock signal to an output terminal, the time between when the data clock signal changes states and when the time adjusted data clock signal changes states determined by the control signals received at the control inputs, the adjustable time delay circuit including a plurality of passgates coupled in series with respective delay elements, each of the passgates being selectively controlled by at least one of the control signals to control the phase of the time adjusted data clock signal relative to the phase of the data clock signal; and a data passing circuit adapted to receive both the data signal and the time adjusted data clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the time adjusted data clock signal changes from the first to the second state.
Claim 23
Dependent Claim
21 words
The circuit of claim 19 wherein the control signals are generated by selectively coupling the control inputs to a reference voltage.
Claim 24
Dependent Claim
68 words
The circuit of claim 19 wherein the: passgates are arranged in columns, each column having a different number of passgates than any other column in the time delay circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective one of the delay elements, the external clock signal coupled to and passing through each of the delay elements.
Claim 25
Dependent Claim
50 words
The circuit of claim 21 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 26
Dependent Claim
17 words
The circuit of claim 19 wherein the synchronous memory circuit is a synchronous static random access memory.
Claim 27
Independent Claim
129 words
A method of adjusting the time that data is delivered to an output terminal of a memory circuit after the memory circuit has been fabricated, the method comprising the steps of: accepting a data signal at a data input; accepting a clock signal at a clock input; selecting a delay time to be added to the clock signal to generate a delayed clock signal, the delay time being selected by selectively coupling control inputs to a control voltage, the control inputs coupled to and controlling a plurality of passgates such that for any single pattern of coupled control inputs, there exists only one path through a controllable delay circuit; and using the delayed clock signal to control the time when the data signal is passed to a data output.
Claim 28
Independent Claim
129 words
A method of adjusting the time that data is delivered to an output terminal of a memory circuit after the memory circuit has been fabricated, the method comprising the steps of: accepting a data signal at a data input; accepting a clock signal at a clock input; selecting a delay time to be added to the clock signal to generate a delayed clock signal, the delay time being selected by selectively coupling control inputs to a control voltage, the control inputs coupled to and controlling a plurality of passgates such that for any single pattern of coupled control inputs, there exists only one path through a controllable delay circuit; and using the delayed clock signal to control the time when the data signal is passed to a data output.
Claim 29
Dependent Claim
19 words
The method of claim 24 wherein the delay time selected is one of a plurality of pre-selected delay times.
Claim 30
Dependent Claim
58 words
The method of claim 24 wherein the step of selecting a delay time further includes the step of selectively coupling control inputs to a control voltage, the control inputs coupled to and controlling a plurality of the passgates such that for any single pattern of coupled control inputs, there exists only one path through a controllable delay circuit.
References Cited (Backward Citations)
US3633174A
Cited
US4096402A
Cited
US4077016A
Cited
US4524448A
Cited
US4404474A
Cited
US4481625A
Cited
US4511846A
Cited
US4508983A
Cited
US4603320A
Cited
US4638451A
Cited
US4514647A
Cited
US4573017A
Cited
US4687951A
Cited
US4600895A
Cited
US4638187A
Cited
US4638187B1
Cited
US4789796A
Cited
US4818995A
Cited
US5636163A
Cited
US4953128A
Cited
US4773085A
Cited
US4972470A
Cited
US5086500A
Cited
US4893087A
Cited
US4984204A
Cited
US5367649A
Cited
US4902986A
Cited
US4902986B1
Cited
US5020023A
Cited
US5555429A
Cited
US5075569A
Cited
US4958088A
Cited
US5165046A
Cited
US5179298A
Cited
US5087828A
Cited
US5408640A
Cited
US5239206A
Cited
US5513327A
Cited
US5473575A
Cited
US6101152A
Cited
US5243703A
Cited
US6067592A
Cited
US5657481A
Cited
US5038115A
Cited
US5134311A
Cited
US5233564A
Cited
US5416909A
Cited
US5926436A
Cited
US5122690A
Cited
US5257294A
Cited
US5311483A
Cited
US5281865A
Cited
US5128563A
Cited
US5223755A
Cited
US5500808A
Cited
US5150186A
Cited
US5128560A
Cited
US5220208A
Cited
US5256989A
Cited
US5212601A
Cited
US5289580A
Cited
US5341405A
Cited
US5194765A
Cited
US5276642A
Cited
US5440260A
Cited
US5272729A
Cited
US5465076A
Cited
US5283631A
Cited
US5498990A
Cited
US5315388A
Cited
US5295164A
Cited
US5313431A
Cited
US5321368A
Cited
US5432823A
Cited
US5355391A
Cited
US5233314A
Cited
US5361002A
Cited
US5278460A
Cited
US5390308A
Cited
US5379299A
Cited
US5254883A
Cited
US5485490A
Cited
US5410263A
Cited
US5572722A
Cited
US5268639A
Cited
US5274276A
Cited
US5532714A
Cited
US5473274A
Cited
US5416436A
Cited
US5448193A
Cited
US5311481A
Cited
US5420544A
Cited
US5539345A
Cited
US5347177A
Cited
US5544203A
Cited
US5430408A
Cited
US5444667A
Cited
US5488321A
Cited
US5347179A
Cited
US5304952A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-30 | 2005-01-29 | 2005-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-30 | 2009-01-29 | 2009-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-30 | 2013-01-29 | 2013-07-31 | $7700.00 | Window Closed / Lapsed |