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US5963735A Expired / Lapsed US ⏱️ 0.0 years remaining

Hardware logic emulation system

Assignee: Quickturn Design Systems Inc
•
Filing: 1997-05-29
•
Granted: 1999-10-05
•
Expires: 2017-05-29
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Abstract

Abstract A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Inventors

  • 👤 Stephen P. Sample
  • 👤 Michael R. D'Amour
  • 👤 Thomas S. Payne

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 02:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 154 words
An hardware logic emulation system comprising: a printed circuit board having an emulation array disposed thereon, said emulation array comprising: a plurality of first programmable integrated circuits, said first programmable integrated circuits having programmable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements; at least one second programmable integrated circuit, said second programmable integrated circuit containing reprogrammable electrical conductors capable of reconfigurably interconnecting selected input/output terminals of selected ones of said plurality of first programmable integrated circuits such that selected functional logic elements in one of said selected ones of said plurality of first programmable integrated circuits containing functional logic elements can be electrically coupled to selected functional logic elements in another of said plurality of said first programmable integrated circuits; and an interface structure including circuitry which provides electrical paths for signals carrying signal information between an external system and said emulation array.
Claim 2
Dependent Claim 154 words
An hardware logic emulation system comprising: a printed circuit board having an emulation array disposed thereon, said emulation array comprising: a plurality of first programmable integrated circuits, said first programmable integrated circuits having programmable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements; at least one second programmable integrated circuit, said second programmable integrated circuit containing reprogrammable electrical conductors capable of reconfigurably interconnecting selected input/output terminals of selected ones of said plurality of first programmable integrated circuits such that selected functional logic elements in one of said selected ones of said plurality of first programmable integrated circuits containing functional logic elements can be electrically coupled to selected functional logic elements in another of said plurality of said first programmable integrated circuits; and an interface structure including circuitry which provides electrical paths for signals carrying signal information between an external system and said emulation array.
Claim 3
Dependent Claim 25 words
The hardware logic emulation system of claim 1 wherein said first programmable integrated circuit and said second programmable integrated circuit comprise programmable gate array devices.
Claim 4
Dependent Claim 28 words
The hardware logic emulation system of claim 2 wherein said first programmable integrated circuit and said second programmable integrated circuit comprise identical types of programmable gate array devices.
Claim 5
Dependent Claim 19 words
The hardware logic emulation system of claim 1 wherein said interface structure is a part of said emulation array.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-10-04 2003-04-05 2003-10-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-10-04 2007-04-05 2007-10-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-10-04 2011-04-05 2011-10-05 $7700.00 Window Closed / Lapsed

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