Visual display logic simulation system

Claim 2

A visual display system comprising means for producing a visual representation of a digital electronic circuit on a display screen by way of a plurality of elements including functional symbols and interconnections therebetween; means for indicating on the screen the logical state of some or all of the constituent parts of the elements of said circuit for specified input conditions to said circuit, wherein said logical state is indicated by way of the manner in which an element is displayed; and control means for varying said indications of logical state in dependence upon variations in the inputs to said circuit and the reaction of the various elements of said circuit to said variations.

Claim 3

The system as recited in claim 1 wherein the indication of logical state is displayed as one of two contrasting colors on said screen.

Claim 4

A visual display system comprising means for producing a visual representation of a digital electronic circuit on a display screen by way of a plurality of elements including functional symbols interconnected at nodes; means for displaying on the screen an indication of the testability value of some or all of the constituent nodes of said circuit wherein said testability is indicated by way of the manner in which the said circuit is displayed at each of said nodes; and control means for varying said indications of testability value in dependence upon variations elsewhere in the electronic circuit.

Claim 5

A visual display system comprising means for producing a visual representation of a digital electronic circuit on a display screen by way of a plurality of elements including functional symbols interconnected at nodes; means for displaying on the screen an indication of the testability value of some or all of the constituent nodes of said circuit wherein said testability is indicated by way of the manner in which the said circuit is displayed at each of said nodes; and control means for varying said indications of testability value in dependence upon variations elsewhere in the electronic circuit.

Claim 6

The system as recited in claim 3 wherein the indication of testability value is displayed as one of a plurality of contrasting colors on said screen.

Claim 7

An improved logic simulation system of the type including a logic simulator responsive to a logical description of a circuit to be simulated and to input and output stimulus data, which logic simulator provides logic state information about the response of the circuit as a function of time; schematic and display formatting means responsive to the logic state information and to schematic element definitions and locations of the circuit to be simulated, for correlating the schematic element definitions and location with the logic state information; and display processor means responsive to the correlated element definition, location and logic state information for converting said information into a visual image, wherein the improvement comprises formatting means responsive to the logic state information and to the schematic element definitions and locations for inserting into the element definition a designation of the color in which the element is to be displayed, which color is representative of the logic state of the element.

Claim 8

An improved logic simulation system of the type including a logic simulator responsive to a logical description of a circuit to be simulated and to input and output stimulus data, which logic simulator provides logic state information about the response of the circuit as a function of time; schematic and display formatting means responsive to the logic state information and to schematic element definitions and locations of the circuit to be simulated, for correlating the schematic element definitions and location with the logic state information; and display processor means responsive to the correlated element definition, location and logic state information for converting said information into a visual image, wherein the improvement comprises formatting means responsive to the logic state information and to the schematic element definitions and locations for inserting into the element definition a designation of the color in which the element is to be displayed, which color is representative of the logic state of the element.

Claim 9

The improved logic simulation system of claim 5, wherein the logical description of the circuit includes the designation of wires which interconnect the logic elements of the circuit, and the logic simulator designates the logic states of the wires as a function of time, and further wherein included among the schematic element definitions are the definitions of the sires which interconnect the logic elements, and further wherein the formatting means modify the schematic element definitions for each wire modified to include a color designation, which designation is representative of its logic state at a selected point in time, so that each wire is displayed in a color which represents the logic state of the wire at the selected point in time.

Claim 10

The improved logic simulation system of claim 6 wherein the formatting means include logic color key means for designating what colors represent what logic states; means responsive to the logic state information designated for each wire and coupled to the logic color key means for selecting the corresponding logic color; and means responsive to the selected logic colors for each wire and to the element definitions for each wire for inserting the logic color information into the element definitions for each wire.

Claim 11

The improved logic simulation system of claim 7, wherein logic one type states are displayed in one color and logic zero type states are displayed in another color.

Claim 12

The improved logic stimulation system of claim 8, wherein logic one type states are displayed in red and logic zero type states are displayed in blue.

Claim 13

The improved logic simulation system of claim 7, wherein unknown logic states and high impedance states of the circuit elements are displayed in different colors.

Claim 14

A logic stimulation system providing a visual display of an electronic circuit being simulated, wherein the electronic circuit is displayed by way of a plurality of interconnected elements, and further wherein the logical states of the elements therein are displayed by displaying the elements in predetermined colors.

Claim 15

A logic stimulation system providing a visual display of an electronic circuit being simulated, wherein the electronic circuit is displayed by way of a plurality of interconnected elements, and further wherein the logical states of the elements therein are displayed by displaying the elements in predetermined colors.

Claim 16

The logic simulation system as recited in claim 11 further including means for displaying design faults in the circuit being simulated.

Claim 17

The logic simulation system as recited in claim 12, wherein the design faults being displayed are designated by a predetermined color.

Claim 18

The logic simulation system as recited in claim 12, wherein the design faults being displayed are designated by an on/off flashing of the fault area.

Claim 19

The logic simulation system as recited in claim 11, further including means for displaying manufacturing fault effects.

Claim 20

The logic simulation system as recited in claim 15, wherein the manufacturing fault effects displayed are designated by predetermined colors.

Claim 21

The logic simulation system as recited in claim 15, wherein the manufacturing fault effects displayed are designated by on/off flashing of the signals carrying the faults.