US4747102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of controlling a logical simulation at a high speed
Assignee: NEC Corp
•
Filing: 1986-03-28
•
Granted: 1988-05-24
•
Expires: 2006-03-28
Abstract
Abstract In a method of controlling a logical simulation of a logic circuit comprising a plurality of logic elements which can be simulated by forming a shift register string, the logical simulation is carried out without serial shift operation of the shift register string on setting shift-in signals into the shift register string and/or on extracting internal states from the shift register string. Setting of the shift-in signals and extraction of the internal states are possible by monitoring a simulation table which has a plurality of addresses for the logic elements.
Inventors
- 👤 Shigehiro Funatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/3183
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
121 words
A method of controlling a logical simulation of a logic circuit comprising a plurality of logic elements which can be simulated by forming a shift register string which is capable of carrying out a serial shift operation, said logical simulation being progressive in accordance with a simulated table on which said logic elements are described, said method comprising the steps of: providing an input stimulation signal for accessing said logic circuit; and controlling operation of said logic elements by the use of said simulation table said controlling step including the step of directly setting said input stimulation signal into said logic elements on said simulation table without said serial shift operation to make said logic circuit carry out said logical simulation.
Claim 2
Independent Claim
121 words
A method of controlling a logical simulation of a logic circuit comprising a plurality of logic elements which can be simulated by forming a shift register string which is capable of carrying out a serial shift operation, said logical simulation being progressive in accordance with a simulated table on which said logic elements are described, said method comprising the steps of: providing an input stimulation signal for accessing said logic circuit; and controlling operation of said logic elements by the use of said simulation table said controlling step including the step of directly setting said input stimulation signal into said logic elements on said simulation table without said serial shift operation to make said logic circuit carry out said logical simulation.
Claim 3
Dependent Claim
177 words
A method as claimed in claim 1, said logic circuit having an output terminal set which is related to said logic elements, wherein: said providing step comprises the steps of: preparing a clock signal pattern of clock signals repeated at every clock period and a level signal pattern of level signals lasting during at least each clock period; detecting whether said input stimulation signal specifies said clock signal pattern or said level signal pattern; and setting said level signals in said shift register string by carrying out said serial shift operation for said logical simulation when said level signal pattern is specified by said input stimulation signal; said controlling step comprising the steps of: driving said logic circuit in accordance with said input stimulation signal to make said logic circuit carry out said logical simulation by directly setting said input stimulation signal into said logic elements on said simulation table; and extracting an output signal set in response to said input stimulation signal from said output terminal set and said logic elements without said serial shift operation.
Claim 4
Dependent Claim
154 words
A method as claimed in claim 1, said logic circuit having an output terminal set which is related to said logic elements, wherein said providing step comprises the steps of: preparing a clock signal pattern of clock signals repeated at every clock period, a level signal pattern of level signals lasting during at least each clock period, and a shift-in pattern of shift-in signals which are to be set in said shift register string; and detecting that said input stimulation pattern is either one of said clock signal pattern, said level signal pattern, and said shift-in pattern; said controlling step comprising the steps of: setting said shift-in signals in said shift register string on said simulation table without said serial logic operation when said shift-in pattern is specified by said input stimulation signal; and producing an output signal set resulting from said shift-in signals by making said logic circuit carry out said logical simulation.
Claim 5
Dependent Claim
45 words
A method as claimed in claim 3, wherein said producing step comprises the steps of: making said logic circuit process said logical simulation by the use of said shift-in signals; and extracting said output signal set from said logic circuit without said serial shift operation.
Claim 6
Dependent Claim
47 words
A method as claimed in claim 3, wherein said producing step comprises the steps of: making said logic circuit process said logical simulation by the use of said shift-in signals; and deriving said output signal set from said logic circuit by carrying out said serial shift operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |