US4945503A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware simulator capable of reducing an amount of information
Assignee: NEC Corp
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Filing: 1987-10-21
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Granted: 1990-07-31
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Expires: 2007-10-21
Abstract
Abstract In a hardware simulator for use in successively carrying out simulations of gates arranged in a logic circuit, a plurality of connection data signals are stored in a connection memory to specify connections among the gates while a plurality of gate species data signals are stored in a gate species memory to represent each species of the gates. Responsive to a test data signal, a processing circuit executes each simulation of the gates with references to both the connection and the gate species data signals read out of the connection memory and the gate species memory, and supplies a simulation result signal to one of several status memories. Each simulation may be carried out in a pipeline fashion. Alternatively, the connection data signals can be derived from a modified logic circuit obtained by rearranging the logic circuit.
Inventors
- 👤 Shigeru Takasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:28
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
285 words
A hardware simulator for use in successively carrying out simulations of a plurality of gates included in a logic circuit, said simulator comprising: connection memory means for storing a plurality of connection data signals which specify connections of said gates and for producing a predetermined number of said connection data signals one at a time; gate species memory means for storing a plurality of gate species data signals representative of species of said gates and for producing a predetermined number of said gate species data signals one at a time; first memory means for storing a plurality of test data signals utilized for simulation of said gates and for successively producing each of said test data signals; simulation execution means, coupled to said connection memory means, said gate species memory means, and said first memory means and responsive to an execution result signal, for executing said simulations of said gates in response to said predetermined number of said connection data signals, and each of said plurality of test data signals with reference to said execution result signal to successively produce a simulation result signal representative of a result of each of said simulations; holding means for holding said simulation result signal; supply means for supplying said simulation result signal held in said holding means to said simulation execution means as said execution result signal; second memory means, coupled to said holding means, for successively storing said simulation result signal and for producing a stored result signal; and signal delivering means, coupled to said first and said second memory means and to said simulation execution means, for selectively delivering one of said each test data signal and said stored result signal to said simulation execution means.
Claim 2
Dependent Claim
285 words
A hardware simulator for use in successively carrying out simulations of a plurality of gates included in a logic circuit, said simulator comprising: connection memory means for storing a plurality of connection data signals which specify connections of said gates and for producing a predetermined number of said connection data signals one at a time; gate species memory means for storing a plurality of gate species data signals representative of species of said gates and for producing a predetermined number of said gate species data signals one at a time; first memory means for storing a plurality of test data signals utilized for simulation of said gates and for successively producing each of said test data signals; simulation execution means, coupled to said connection memory means, said gate species memory means, and said first memory means and responsive to an execution result signal, for executing said simulations of said gates in response to said predetermined number of said connection data signals, and each of said plurality of test data signals with reference to said execution result signal to successively produce a simulation result signal representative of a result of each of said simulations; holding means for holding said simulation result signal; supply means for supplying said simulation result signal held in said holding means to said simulation execution means as said execution result signal; second memory means, coupled to said holding means, for successively storing said simulation result signal and for producing a stored result signal; and signal delivering means, coupled to said first and said second memory means and to said simulation execution means, for selectively delivering one of said each test data signal and said stored result signal to said simulation execution means.
Claim 3
Dependent Claim
142 words
A hardware simulator as claimed in claim 1, wherein said simulation execution means comprises: processing means, coupled to said connection memory means, said gate species memory means, said first memory means, and said supply means, for processing said execution result signal, said predetermined number of said connection data signals, said predetermined number of said gate species data signals, and each of said plurality of test data signals to successively execute each of said simulations and to successively produce said simulation result signal; and control means for controlling said connection memory means, said gate species memory means, said first and second memory means, said supply means, and said processing means to enable said processing means to execute each of said simulations in cooperation with said connection memory means, said gate species memory means, said first and second memory means, and said supply means.
Claim 4
Dependent Claim
78 words
A hardware simulator as claimed in claim 2, wherein said processing means comprises: processing unit means, equal in number to said predetermined number, for individually processing each of said gate species data signals and each of said connection data signals with reference to each of said test data signals and said execution result signal and for producing a processed signal representative of a result of processing; and means for producing said processed signal as said simulation result signal.
Claim 5
Dependent Claim
111 words
A hardware simulator as claimed in claim 3, wherein said processing unit means comprises: logical operation means, responsive to each of said test data signals, each of said connection data signals, and said execution result signal, for carrying out a plurality of logical operations in parallel and for producing operation result signals representative of results of said logical operations; and means, coupled to said logical operation means and responsive to each of said gate species data signals, for producing a selected one of said operation result signals determined by each of said gate species data signals and for producing said selected one of said operation result signals as said processed signal.
Claim 6
Dependent Claim
47 words
A hardware simulator as claimed in claim 1, said logic circuit being divisible into a plurality of levels which are successively connected to one another and each logic level comprising at least one gate, wherein one of said simulations is carried out at each of said levels.
Claim 7
Dependent Claim
101 words
A hardware simulator as claimed in claim 1, each of said simulations being divisible into a plurality of partial simulations, each of said connection data signals being divisible into a plurality of partial connection data signals necessary for respective partial simulations, wherein said connection memory means comprises: a plurality of memory elements for storing said partial connection data signals; selection means coupled to said memory elements for successively selecting said partial connection data signals one by one to successively produce each of said partial connection data signals; and means for producing said partial connection data signals as said connection data signals.
Claim 8
Dependent Claim
39 words
A hardware simulator as claimed in claim 6, wherein said simulation execution means successively carries out said partial simulations to produce as said simulation result signal a sequence of partial result signals representative of results of said partial simulations.
Claim 9
Dependent Claim
113 words
A simulation method of successively carrying out simulations of a plurality of gates included in a logic circuit, said gates having a predetermined arrangement which is divisible into a plurality of levels successively connected from a first level to a last level, said simulation method comprising the steps of: selecting one of said levels as a reference level; modifying said predetermined arrangement with reference to said reference level into a modified arrangement by rearranging said gates of said logic circuit; deriving, from said modified arrangement, connection data signals representative of connections of said gates in said modified arrangement; and successively executing each of said simulations by the use of said connection data signals.
Claim 10
Dependent Claim
113 words
A simulation method of successively carrying out simulations of a plurality of gates included in a logic circuit, said gates having a predetermined arrangement which is divisible into a plurality of levels successively connected from a first level to a last level, said simulation method comprising the steps of: selecting one of said levels as a reference level; modifying said predetermined arrangement with reference to said reference level into a modified arrangement by rearranging said gates of said logic circuit; deriving, from said modified arrangement, connection data signals representative of connections of said gates in said modified arrangement; and successively executing each of said simulations by the use of said connection data signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |