System for testing the failure or satisfactory operation of a circuit having logic components

Claim 1

A system for testing the failure or satisfactory operation of a circuit having logic components, in which n components for a system of components marked l to n in a predetermined manner and interconnected to that said system has on one output a logic state corresponding to the failure or satisfactory operation state of the system and which depends on the failure or satisfactory operating state of each of the n components of the system, each of the n components of the system having at least one simulation input able to receive a signal simulating the failure or satisfactory operation of said system, comprising: a generator whose outputs are respectively connected to the simulation inputs of the components these generator outputs providing simulation signals having a first or a second logic state making it possible to bring one or more components respectively into the failure or satisfactory operation state and then conversely and reciprocally bringing said component or components into a satisfactory operation or failure state, for one or more combinations from among the n components of the system; testing means connected to the output of the system and able to mark the logic level of the output signal of the system, these testing means comprising: a counter having a loading input for loading a predetermined value corresponding to numbers of components to be simulated in the tested circuit, said counter having another input connected to an output of the generator for receiving an initialization signal on initializing the generator, and another input connected to an output of the generator providing a control pulse for controlling the countdown of said counter, an output of said counter being connected to a stop control signal input of the generator for providing a signal to the generator when all the components have been simulated; another counter connected to an output of the genertor for receiving a resetting signal, on initializing the generator and another input connected to the generator output for receiving such control pulse for controlling the incrementation of the counter content; means for marking the logic level of the output signal of the system said means connected to the system output and to an output of the generator for receiving a synchronizing signal for each new combination of simulation signals, and connected to an output of said counter for marking the number of any component for which the change of logic level of the simulation signal applied thereto beings about a change of level of the output signal of the system.

Claim 2

A system for testing the failure or satisfactory operation of a circuit having logic components, in which n components for a system of components marked l to n in a predetermined manner and interconnected to that said system has on one output a logic state corresponding to the failure or satisfactory operation state of the system and which depends on the failure or satisfactory operating state of each of the n components of the system, each of the n components of the system having at least one simulation input able to receive a signal simulating the failure or satisfactory operation of said system, comprising: a generator whose outputs are respectively connected to the simulation inputs of the components these generator outputs providing simulation signals having a first or a second logic state making it possible to bring one or more components respectively into the failure or satisfactory operation state and then conversely and reciprocally bringing said component or components into a satisfactory operation or failure state, for one or more combinations from among the n components of the system; testing means connected to the output of the system and able to mark the logic level of the output signal of the system, these testing means comprising: a counter having a loading input for loading a predetermined value corresponding to numbers of components to be simulated in the tested circuit, said counter having another input connected to an output of the generator for receiving an initialization signal on initializing the generator, and another input connected to an output of the generator providing a control pulse for controlling the countdown of said counter, an output of said counter being connected to a stop control signal input of the generator for providing a signal to the generator when all the components have been simulated; another counter connected to an output of the genertor for receiving a resetting signal, on initializing the generator and another input connected to the generator output for receiving such control pulse for controlling the incrementation of the counter content; means for marking the logic level of the output signal of the system said means connected to the system output and to an output of the generator for receiving a synchronizing signal for each new combination of simulation signals, and connected to an output of said counter for marking the number of any component for which the change of logic level of the simulation signal applied thereto beings about a change of level of the output signal of the system.