Computer-aided automatic wiring method for semiconductor integrated circuit device

Claim 1

An automatic wiring method for a semiconductor integrated circuit device in which function blocks selected to obtain desired logical functions are arranged on a substrate and channels are defined around the function blocks to serve as wiring regions, said method comprising the steps of: (a) selecting a first channel from the channels on said substrate in accordance with a predetermined processing order; (b) performing routing/wiring processing to determine electrical connecting paths between associated function blocks in said first channel in accordance with a bonding request, thereby obtaining a normal wiring pattern; (c) detecting, after the routing/wiring processing is completed, a second channel which neighbors said first channel and has been already subjected to normal routing/wiring processing, said second channel having a processing order immediately before a processing order of said first channel; (d) merging said first and second channels to form a new third channel, the area of which is expanded, said third channel having a combined wiring pattern obtained by combining wiring patterns of said first and second channels; (e) performing wiring pattern rearranging to modify said combined wiring pattern of said third channel to matching with the shortest routing rule at an expanded space of said third channel; and (f) verifying whether a vacant space not contributing to wiring is left in the modified wiring pattern of said third channel, and if such a vacant space is detected, removing the vacant space to reduce the area of said third channel, thereby to optimize the entire wiring pattern of said integrated circuit device and maximize packing density of said integrated circuit device.