Field programmable device with circuitry for detecting poor insulation between adjacent word lines

Claim 1

A field programmable device comprising: a semiconductor substrate; a plurality of word lines, each of said word lines comprising a semiconductor layer of a first conductivity type formed on said semiconductor substrate, said word lines being isolated from each other; an insulating layer formed on said semiconductor layer and having a plurality of windows formed therein; a plurality of regular memory cells, each of which has a first impurity region of a second conductivity type, opposite to said first conductivity type, formed in said semiconductor layer, and a second impurity region, of said first conductivity type, formed in said first impurity region; a plurality of regular bit lines intersecting said plurality of word lines, each of said regular bit lines comprising a conductive layer formed on said insulating layer, said conductive layers contacting said second impurity regions of said regular memory cells through said windows; at least one test bit line positioned adjacent to one of said plurality of regular bit lines and intersecting said plurality of word lines, said at least one test bit line comprising a test conductive layer formed on said insulating layer; and a plurality of test memory cells respectively formed at the intersections of said at least one test bit line and said plurality of word lines, said plurality of test memory cells including first test memory cells and second test memory cells which are formed at alternating intersections, each of said first test memory cells having a first impurity region of said second conductivity type formed in said semiconductor layer, and a second impurity region of said first conductivity type formed in said first impurity region, each of said second test memory cells including a first impurity region of said second conductivity type formed in said semiconductor layer, said test bit line being in contact with said second impurity regions of said first test memory cells through said windows in said insulating layer, so that said second impurity regions of said first test memory cells are in contact with said at least one test bit line to form conducting test memory cells, said second test memory cells being electrically insulated from said at least one test bit line by said insulating layer, so that said second test memory cells form non-conducting test memory cells.