Incremental logic synthesis method

Claim 2

An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit which performs up-dated functions of current functions which are performed by a current gate-level logic circuit so that part thereof is used in the up-dated circuit, wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by a computer for performing the current functions, said method comprising the steps of: (a) synthesizing an intermediate gate-level logic circuit which performs the up-dated functions, in response to input data describing the up-dated functions; (b) synthesizing the up-dated circuit in response to data describing the synthesized intermediate circuit and to data describing the current circuit, wherein the synthesizing step includes the steps of (b1) identifying a corresponding-portion pair which includes a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first and second portions are mutually equivalent, and (b2) combing the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.

Claim 3

An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit having a plurality of gates, wherein the updated circuit performs up-dated functions of current functions performed by a current gate-level logic circuit having a plurality of gates such that a part of said current circuit is used in the up-dated circuit, and wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by said computer for performing the current functions, said original circuit having a plurality of gates, said method comprising the steps of: (a) synthesizing in response to input data describing the up-dated functions an intermediate gate-level logic circuit having a plurality of gates, wherein said intermediate circuit performs the up-dated functions; and (b) synthesizing the up-dated circuit in response to data describing the synthesized intermediate circuit and the current circuit; wherein the step of synthesizing the up-dated circuit includes the steps of (b1) identifying a pair of corresponding-portions which comprises a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first portion can perform identical logical operations on identical input signals and provide identical output signals, identical to the second portion, and (b2) combining the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.

Claim 4

An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit having a plurality of gates, wherein the updated circuit performs up-dated functions of current functions performed by a current gate-level logic circuit having a plurality of gates such that a part of said current circuit is used in the up-dated circuit, and wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by said computer for performing the current functions, said original circuit having a plurality of gates, said method comprising the steps of: (a) synthesizing in response to input data describing the up-dated functions an intermediate gate-level logic circuit having a plurality of gates, wherein said intermediate circuit performs the up-dated functions; and (b) synthesizing the up-dated circuit in response to data describing the synthesized intermediate circuit and the current circuit; wherein the step of synthesizing the up-dated circuit includes the steps of (b1) identifying a pair of corresponding-portions which comprises a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first portion can perform identical logical operations on identical input signals and provide identical output signals, identical to the second portion, and (b2) combining the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.

Claim 5

A method according to claim 2, wherein the combining step includes a step of assigning to a respective gate and a respective interconnecting signal line included within the portion other than the second portion, within the intermediate circuit, a respective gate identification name and a respective signal line identification name which are not identical to gate identification names and signal line identification names assigned to gates and interconnecting signal lines included in the first portion within the current circuit.

Claim 6

A method according to claim 2, wherein the current circuit is a circuit obtained by modifying the original circuit so as to be adapted to operate within practical limits set by the physical characteristics of the gates.

Claim 7

A method according to claim 2, wherein the current circuit is a circuit obtained by replacing at least one of the gates included in the original circuit by another gate which can perform the same logical operation on an input signal thereto as the one gate.

Claim 8

A method according to claim 5, wherein the current circuit is a circuit obtained by mutually exchanging pins of one of the gates included in the original circuit so that a signal supplied to or from a pin of the one gate is supplied to or from a pin not corresponding to a pin of a corresponding gate of the current circuit.

Claim 9

A method according to claim 2, wherewith identifying step includes a step of identifying corresponding-gate pairs each comprising a first gate belonging to the first portion of the current circuit and a second gate belonging to the second portion of the intermediate circuit, wherein the first gate can perform one or a plurality of same logical operations on one or a plurality of same input signals and provides one or a plurality of same output signals, as the second gate.

Claim 10

A method according to claim 7, wherein the combining step includes a step of combining gates of the current circuit, belonging to the identified corresponding-gate pairs with gates of the intermediate circuit, not belonging to the identified corresponding-gate pairs.

Claim 11

A method according to claim 7, wherein the identifying step of corresponding-gate pairs includes a step of: identifying as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate pair satisfies a predetermined condition on an input gate which is a gate directly connected to an input pin of the first gate and on a gate connected to an input pin of the second gate.

Claim 12

A method according to claim 7, wherein the identifying step of the corresponding-gate pairs includes a step of: identifying, as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when a first group of gates of the current circuit, comprising the first gate and one or plural other gates connected to the first gate and a second group of gates of the intermediate circuit, comprising the second gate and one or plural gates connected to the second gate satisfy a condition predetermined on logical operations performed by the first and second group and on kinds of physical characteristics of gates belonging to the first and second group.

Claim 13

A method according to claim 7, wherein the identifying step of the pair of corresponding-portions further includes a step of: identifying corresponding-pin pairs for a respective one of the identified corresponding-gate pairs, wherein a respective corresponding-pin pair comprises first and second pins, wherein the first pin is included in a first gate of the current circuit, belonging to one of the identified corresponding-gate pairs and the second pin is included in a second gate of the intermediate circuit, belonging to the one corresponding-gate pair, wherein the first and second pins are pins for a same input or output signal.

Claim 14

A method according to claim 11, wherein the identifying step of the pair of corresponding-portions further includes a step of: identifying corresponding-subgate pairs for a respective gate-pair belonging to the identified corresponding-gate pairs and comprising a first composite gate belonging to the current circuit and a second composite gate belonging to the intermediate circuit, wherein a respective corresponding-subgate pair comprises a first subgate belonging to the first composite gate and a second subgate belonging to the second composite gate, and wherein the first subgate can perform a same logical operation on one or a plurality of same input signals and provide one or a plurality of same output signals, as the second subgate.

Claim 15

A method according to claim 12, wherein the identifying step of corresponding-pin pairs includes a step of identifying corresponding-pin pairs for a respective corresponding-subgate pair.

Claim 16

A method according to claim 7, wherein the identifying step of corresponding-gate pairs includes a step of: identifying as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate pair satisfies a predetermined condition on a gate connected to an output pin of the first gate and on a gate connected to an output pin of the second gate.

Claim 17

A method according to claim 14, wherein the predetermined condition comprises a first condition on an output gate of the first gate and on an output gate of the second gate, wherein the output gate of the first gate is a gate directly connected to an output pin of the first gate and wherein the output gate of the second gate is a gate directly connected to an output pin of the second gate.

Claim 18

A method according to claim 15, wherein the first condition comprises a second condition on a common output corresponding-gate pair for the first and second gates, wherein the pair comprises an output gate of the first gate and on output gate of the second gate which have already been identified as belonging to one of the corresponding-gate pairs.

Claim 19

A method according to claim 16, wherein the second condition comprises a third condition on a total number of one or plural common output corresponding-gate pairs for the first and second gates.

Claim 20

A method according to claim 17, wherein the third condition comprises a fourth condition on a first sum(N OG (G I )) of a total number of one or plural output gates of the first gate and a total number of one or plural primary output signals supplied from the first gate from outside of the current circuit, on a second sum (N OG (G J )) of a total number of one or plural output gates of the second gate and a total number of one or plural primary output signals supplied from the second gate to outside of the intermediate circuit, and on a third sum (N COG (G I , G J )) of a total number of one or plural common output corresponding-gate pairs and a total number of one or plural common primary output signals supplied to the first gate and one or plural primary output signals supplied to the first gte and one or plural primary output signals supplied to the second gate.

Claim 21

A method according to claim 18, wherein the fourth condition comprises a fifth condition on a common output gate ratio which is dependent on a first ratio of the third sum (N COG (G I , G J )) to the first sum (N OG (G I )) and on a second ratio of the third sum (N COG (G I , G J )) to the second sum (N CIG (G I ).

Claim 22

A method according to claim 19, wherein the common output gate ratio is dependent on a sum of the first and second ratios.

Claim 23

A method according to claim 7, wherein the identifying step of the corresponding-gate pairs includes a step of: identifying, as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate-pair satisfies a predetermined condition on both an input signal supplied to the first gate and an input signal supplied to the second gate.

Claim 24

A method according to claim 21, wherein the predetermined condition comprises a first condition on both a primary input signal supplied to the first gate from outside of the current circuit and a primary input signal supplied to the second gate from outside of the intermediate circuit.

Claim 25

A method according to claim 22, wherein the first condition includes a second condition on a common primary input signal of the first and second gates which is a primary input signal belonging to both of one or a plurality of input signals supplied to the first gate and one or a plurality of primary input signals supplied to the second gate.

Claim 26

A method according to claim 23, wherein the second condition includes a third condition on a total number of one or a plurality of common primary input signal of the first and second gates.

Claim 27

A method according to claim 24, wherein the third condition comprises a fourth condition on a first total number (N IS (G I )) of one or a plurality of primary input signals supplied to the first gate, a second total number (N IS (G J )) of one or a plurality of primary input signals supplied to the second gate and a third total number (N CIS (G I , G J )) of one or a plurality of common primary input signals of the first and second gates.

Claim 28

A method according to claim 25, wherein the fourth condition comprises a fifth condition on a common primary input signal ratio (R CIS (G I , G J )) which is dependent on a first ratio of the third total number (N CIS (G I , G J )) to the first total number (N CIS (G I )) and upon a second ratio of the third total number (N CIS (G I , G J )) to the second total number (N IS (G J )).

Claim 29

A method according to claim 26, wherein the common primary input signal ratio (R CIS (G I , G J )) is dependent on a sum of the first and second ratios.

Claim 30

A method according to claim 27, wherein the identifying step of a gate-pair as one of corresponding gate pairs based upon the fifth condition is carried out under a condition that a total number of primary input signals supplied to the intermediate circuit from outside thereof is larger than a total number of primary output signals supplied from the intermediate circuit to outside thereof.

Claim 31

A method according to claim 7, wherein the identifying step of the corresponding-gate pairs includes a step of: identifying as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate pair satisfies a predetermined condition on an output signal supplied from the first gate and on an output signal supplied from the second gate.

Claim 32

A method according to claim 29, wherein the predetermined condition comprises a first condition on both a primary output signal supplied from the first gate to outside of the current circuit and a primary output signal supplied from the second gate to outside of the intermediate circuit and does not include a condition on an interconnecting output signal supplied from the first gate to another gate of the current circuit nor a condition on an interconnecting output signal supplied from the second gate to another gate of the intermediate circuit.

Claim 33

A method according to claim 30, wherein the first condition includes a second condition on a common primary output signal of the first and second gates which is a primary output signal belonging to both of primary one or a plurality of output signals supplied from the first gate and one or a plurality of primary output signals supplied from the second gate.

Claim 34

A method according to claim 31, wherein the second condition includes a third condition on a total number of one or a plurality of common primary output signals of the first and second gates.

Claim 35

A method according to claim 32, wherein the third condition comprises a fourth condition on a first total number (N OS (G I )) of one or a plurality of primary output signals supplied from the first gate to outside of the current circuit, a second total number (N OS (G J )) of one or a plurality of primary output signals supplied from the second gate to outside of the intermediate circuit and a third total number of one or a plurality of common primary output signals of the first and second gates.

Claim 36

A method according to claim 33, wherein the fourth condition comprises a fifth condition on a common primary output signal ratio which is dependent upon a first ratio of the third total number to the first total number and upon a second ratio of the third total number to the second total number.

Claim 37

A method according to claim 34, wherein the common primary output signal ratio (R COS (G I , G J )) is dependent on a sum of the first and second ratios.

Claim 38

A method according to claim 35, wherein the identifying step of a gate-pair as one of corresponding gate pairs based upon the fifth condition is carried out under a condition that a total number of primary input signals supplied to the intermediate circuit from outside thereof is less than a total number of primary output signals supplied from the intermediate circuit to outside thereof.

Claim 39

A method according to claim 36, wherein the predetermined condition comprises a first condition on an input gate of the first gate and on an input gate of the second gate, wherein the input gate of the first gate is a gate directly connected to an input pin of the first gate and wherein the input gate of the second gate is a gate directly connected to an input pin of the second gate.

Claim 40

A method according to claim 37, wherein the first condition comprises a second condition on a common input corresponding-gate pair for the first and second gates, wherein the pair comprises an input gate of the first gate and an input gate of the second gate which have already been identified as belonging to one of the corresponding-gate pairs.

Claim 41

A method according to claim 38, wherein the second condition comprises a third condition on a total number of one or plural common input corresponding-gate pairs for the first and second gates.

Claim 42

A method according to claim 39, wherein the third condition comprises a fourth condition on a first sum (N IG (G I )) of a total number of one or plural input gates of the first gate and a total number of one or plural primary input signals supplied to the first gate from outside of the current circuit, on a second sum ((N IG (G J )) of a total number of one or plural input gates of the second gate and a total number of one or plural primary input signals supplied to the second gate form outside of the intermediate circuit, and on a third sum (N CIG (G I , G J )) of a total number of one or plural common input corresponding-gate pairs and a total number of one or plural common primary input signals of the first and second gates each of which is a primary input signal belonging to both of one or plural primary input signals supplied to the first gate and one or plural primary input signals supplied to the second gate.

Claim 43

A method according to claim 40, wherein the fourth condition comprises a fifth condition on a common input gate ratio which is dependent on a first ratio of the third sum (N CIG (G I , G J )) to the first sum (N IG (G I )) and on a second ratio of the third sum (N CIG (G I , G J )).

Claim 44

A method according to claim 41, wherein the common input gate ratio is dependent on a sum of the first and second ratios.

Claim 45

An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit which performs up-dated functions of current functions which are performed by a current gate-level logic circuit so that part thereof is used in the up-dated circuit, wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by a computer for performing the current functions, said method comprising the steps of: (a) synthesizing an intermediate gate-level logic circuit which performs the up-dated functions, in response to input data describing the up-dated functions; (b) synthesizing an up-dated circuit in response to data describing the synthesized intermediate circuit and to data describing the current circuit, wherein the synthesizing step includes a step of (b1) identifying a corresponding-portion pair which includes a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first portion can be used in place of the second portion, and (b2) combining the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.

Claim 46

An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit which performs up-dated functions of current functions which are performed by a current gate-level logic circuit so that part thereof is used in the up-dated circuit, wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by a computer for performing the current functions, said method comprising the steps of: (a) synthesizing an intermediate gate-level logic circuit which performs the up-dated functions, in response to input data describing the up-dated functions; (b) synthesizing an up-dated circuit in response to data describing the synthesized intermediate circuit and to data describing the current circuit, wherein the synthesizing step includes a step of (b1) identifying a corresponding-portion pair which includes a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first portion can be used in place of the second portion, and (b2) combining the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.

Claim 47

A method according to claim 43, wherein the identifying step includes a step of: identifying corresponding-gate pairs each including a first gate which should belong to the first portion of the current circuit and a second gate which should belong to the second portion of the intermediate circuit, wherein the first gate can be used in place of the second gate.

Claim 48

A method according to claim 44, wherein the combining step includes a step of: combining gates of the current circuit, belonging to the identified corresponding-gate pairs with gates of the intermediate circuit, not belonging to the identified corresponding-gate pairs.

Claim 49

A method according to claim 44, wherein the identifying step of the corresponding-portion pair further includes a step of: identifying corresponding-subgate pairs for a respective gate-pair belonging to the identified corresponding-gate pairs and including a first composite gate belonging to the current circuit and a second composite gate belonging to the intermediate circuit, wherein a respective corresponding-subgate pair comprises a first subgate belonging to the first composite gate and a second subgate belonging to the second composite gate, and wherein the first subgate can be used in place of the second subgate.

Claim 50

A method according to claim 46, wherein the identifying step of the corresponding-portion pair further includes a step of: identifying corresponding-pin pairs for a respective one of already identified corresponding-gate pairs, wherein a respective corresponding-pin pair comprises first and second pins, wherein the first pin is included in a first gate of the current circuit, belonging to one of the identified corresponding-gate pairs and the second pin is included in a second gate of the intermediate circuit, belonging to the one corresponding-gate pair, wherein the first and second pins which can be used in place of each other.

Claim 51

A method according to claim 44 wherein the identifying step of the corresponding gate pairs includes a step of: identifying, as one of the corresponding-gate pairs a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate pair satisfies one of a first predetermined condition on a primary input signal supplied to the first gate from outside of the current circuit and a primary input signal supplied to the second gate from outside of the intermediate circuit and a second predetermined condition on a primary output signal supplied from the first gate to outside of the current circuit and a primary output signal supplied from the second gate to outside of the intermediate circuit.

Claim 52

A method according to claim 48, wherein the first and second conditions respectively comprises a condition on a common primary input signal ratio (R CIS (G I , G J )) and a condition on a common primary output signal ratio (R COS (G I , G J )) for the gate pair, wherein the common primary input signal ratio ((R CIS (G I , G J )) is dependent on a sum of a first ratio of a first total number (N CIS (G I , G J )) to a second total number (N IS (G I )) and a second ratio of the first total number (N CIS (G I , G J )) to a third total number (N CIS (G I ), and a number of one or plural common primary input signals of the first and second gates, wherein the first total number (N CIS (G I , G J )) is total number of one or plural of common primary input signals of the first and second gates, wherein a respective common primary input signal of the first and second gates is a primary input signal belonging to both of one or plural primary input signals supplied to the first gate and one or plural primary input signals supplied to the second gate, wherein the second total number (N IS (G I )) is a total number of one or plural primary input signals supplied to the first gate from outside of the current circuit, wherein the third total number (N IS (G J )) is a total number of one or plural primary input signals supplied to the second gate from outside of the intermediate circuit, and wherein the common primary output signal ratio (R COS (G I , G J )) is dependent upon a sum of a first ratio of a fourth total number (N COS (G I , G J )) to a fifth total number (N OS (G I )) and a second ratio of the fourth total number (N COS (G I G J )) to a sixth total number (N OS (G J )), wherein the fourth total number (N COS (G I , G J )) is a total number of one or plural common primary output signals of the first and second gates, wherein a respective common primary output signal of the first and second gates is a primary output signal belonging to both of one or plural primary output signals supplied from the first gate and one or plural primary output signals supplied from the second gate, wherein the fifth total number (N OS (G I )) is a total number of one or plural primary output signals supplied from the first gate to outside of the current circuit, and wherein the sixth total number (N OS (G J )) is a total number of one or plural primary output signals supplied from the second gate to outside of the intermediate circuit.

Claim 53

A method according to claim 49, wherein one of the first and second predetermined conditions is selected, depending upon whether or not a total number of primary input signals supplied to the intermediate circuit from outside thereof is larger than a total number of primary output signals supplied from the intermediate circuit to outside thereof.

Claim 54

A method according to claim 48, wherein the identifying step of corresponding-gate pairs further includes a step of: identifying as one of the corresponding-gate pairs, a respective gate pair comprising a first gate belonging to the current circuit and a second gate belonging to the intermediate circuit, when the gate pair does not satisfy the one of the first and second conditions but satisfies a predetermined condition on one or plural gates directly connected to the first gate and on one or plural gates directly connected to the second gate.

Claim 55

A method according to claim 51, wherein the predetermined condition is one of third and fourth conditions, wherein the third condition is a condition on an output gate of the first gate and an output gate of a second gate, wherein the output gate of the first or second gate is a gate directly connected to an output pin of the first or second gate, wherein the fourth condition is a condition on an input gate of the first gate and an input gate of the second gate, wherein the input gate of the first or second gate is a gate directly connected to an input pin of the first or second gate.

Claim 56

A method according to claim 54, wherein one of the first and second predetermined conditions is selected, depending upon whether or not a total number of primary input signals supplied to the intermediate circuit from outside thereof is larger than a total number of primary output signals supplied from the intermediate circuit to outside thereof, wherein, when the second condition is selected, the identifying step of a corresponding-gate pair is first done based upon the fourth condition and thereafter the same step is further done based upon the third condition, for a gate pair not identified as a corresponding-gate pair in the identifying step which is based upon the fourth condition.

Claim 57

A method according to claim 52, wherein the third condition is a condition on a common output gate ratio which is dependent on a sum of a first ratio of a first sum (N COG (G I , G J )) to a second sum (N OG (G I ) and on a second ratio of the first sum (N COG (G I , G J )) to a third sum (N OG (G J )), wherein the first sum (N COG (G I , G J )) is sum of a total number of one or plural common output corresponding-gate pairs and a total number of one or plural common primary output signals of the first and second gates each of which is a primary output signal belonging to both of one or plural primary output signals supplied to the first gate and one or plural primary output signals supplied to the second gate, wherein the second sum (N OG (G I )) is a sum of a total number of one or plural output gates of the first gate and a total number of one or plural primary output signals supplied from the first gate to outside of the current circuit, and wherein the third sum (N OG (G J )) is a sum of a total number of one or plural output gates of the second gate and a total number of one or plural primary output signals supplied from the second gate to outside of the intermediate circuit, wherein the fourth condition is a condition on a common input gate ratio which is dependent on a sum of a third ratio of a fourth sum (N CIG (G I , G J )) to a fifth sum (N IG (G J )) and on a fourth ratio of the fourth sum (N CIG (G I , G J )) to a sixth sum (N IG (G J )), wherein the fourth sum (N CIG (G I , G J )) is a sum of a total number of one or plural common input corresponding-gate pairs and a total number of one or plural common primary input signals of the first and second gates each of which is a primary input signal belonging to both of one or plural primary input signals supplied to the first gate and one or plural primary input signals supplied to the second gate, wherein the fifth sum (N IG (G I )) is a sum of a total number of one or plural input gates of the first gate and a total number of one or plural primary input signals supplied to the first gate from outside of the current circuit, wherein the sixth sum (N IG (G J )) is a sum of a total number of one or plural input gates of the second gate and a total number of one or plural primary input signals supplied to the second gate from outside of the intermediate circuit.

Claim 58

A method according to claim 54, wherein one of the first and second predetermined conditions is selected, depending upon whether or not a total number of primary input signals supplied to the intermediate circuit from outside thereof is larger than a total number of primary output signals supplied from the intermediate circuit to outside thereof, wherein, when the first condition is selected, the identifying step of a corresponding-gate pair is first done based upon the third condition and thereafter the same step is further done based upon the fourth condition, for a gate pair not identified as a corresponding-gate pair in the identifying step which is based upon the third condition.