US4901259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asic emulator
Assignee: LSI Corp
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Filing: 1988-08-15
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Granted: 1990-02-13
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Expires: 2008-08-15
Abstract
Abstract Disclosed is a simulation model which facilitates the "real-time" simulation of application specific integrated circuits (ASICs) in the actual digital computer system in which they will be incorporated. Significantly, this invention permits the emulation of an ASIC device, and thus does not require the fabrication of an actual physical specimen of that device. Instead, this invention permits the use of a software model which facilitates debugging of the ASIC device and permits effective generation of system test vectors. Such an approach facilitates the system-level testing of ASIC devices prior to fabrication, by permitting both the generation of system test vectors and the debugging of the internal behavior of such ASIC devices without limiting the flexibility, with respect to other devices in the system, of either simulating such devices in software or utilizing actual physical specimens of such devices.
Inventors
- 👤 Daniel R. Watkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/318307; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
330 words
A structure for modeling the operation of a specified computing device in a target system, said structure comprising a computer for executing a software model of said specified computing device, said specified computing device not being physically present in said target system, said software model comprising software input pin means for receiving one or more software input pin signals representing the signals received as inputs to said specified computing device, software output pin means for transmitting one or more software output pin signals representing the signals generated as outputs of said specified computing device, and software modeling means for modeling in software the execution of said specified computing device, by which software input pin signals are transformed into software output pin signals, a target system comprising one or more physical computing devices physically present in said target system, and a dummy package placed in the target system where said specified computing device, once fabricated, is intended to be placed, said dummy package comprising bidirectional hardware input/output pin means for receiving as input and transmitting as output both hardware input pin signals, representing the signals generated as inputs to said specified computing device, and hardware output pin signals, representing the signals generated as outputs of said specified computing device, input synchronization means, operationally connected to said computer and said target system, for receiving hardware input pin signals from said target system and transforming said hardware input pin signals into software input pin signals by synchronizing the bidirectional hardware input/output pin means of said dummy package with the software input pin means of the software model of said specified computing device, and output synchronization means, operationally connected to said computer and said target system, for receiving software output pin signals from said computer and transforming said software output pin signals into hardware output pin signals by synchronizing the software output pin means of the software model of said specified computing device with the bidirectional hardware input/output pin means of said target system.
Claim 2
Dependent Claim
330 words
A structure for modeling the operation of a specified computing device in a target system, said structure comprising a computer for executing a software model of said specified computing device, said specified computing device not being physically present in said target system, said software model comprising software input pin means for receiving one or more software input pin signals representing the signals received as inputs to said specified computing device, software output pin means for transmitting one or more software output pin signals representing the signals generated as outputs of said specified computing device, and software modeling means for modeling in software the execution of said specified computing device, by which software input pin signals are transformed into software output pin signals, a target system comprising one or more physical computing devices physically present in said target system, and a dummy package placed in the target system where said specified computing device, once fabricated, is intended to be placed, said dummy package comprising bidirectional hardware input/output pin means for receiving as input and transmitting as output both hardware input pin signals, representing the signals generated as inputs to said specified computing device, and hardware output pin signals, representing the signals generated as outputs of said specified computing device, input synchronization means, operationally connected to said computer and said target system, for receiving hardware input pin signals from said target system and transforming said hardware input pin signals into software input pin signals by synchronizing the bidirectional hardware input/output pin means of said dummy package with the software input pin means of the software model of said specified computing device, and output synchronization means, operationally connected to said computer and said target system, for receiving software output pin signals from said computer and transforming said software output pin signals into hardware output pin signals by synchronizing the software output pin means of the software model of said specified computing device with the bidirectional hardware input/output pin means of said target system.
Claim 3
Dependent Claim
149 words
The structure of claim 1 also comprising one or more software models of additional software-modeled computing devices not physically present in said computer system, each of said software models capable of being executed by said computer and comprising software input means, software output pin means and software modeling means corresponding to the computing device being modeled, a dummy package for each computing device being modeled in software, said dummy package comprising bidirectional hardware input/output means for receiving as input and transmitting as output both hardware input pin signals and hardware output pin signals, and control means for converting software pin output signals from said computer, representing the signals generated as outputs from said specified computing device or from one of said additional software-modeled computing devices, into software pin input signals for said computer, representing the signals generated as inputs to another of said specified and additional software-modeled computing devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |