US4763288A
Expired / Lapsed
US
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System for simulating electronic digital circuits
Assignee: Schlumberger Systems and Services Inc
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Filing: 1985-12-31
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Granted: 1988-08-09
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Expires: 2005-12-31
Abstract
Abstract A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor. The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs. When the circuit is simulated, the start time and finish time for each component is determined, giving the execution time for the circuit. Output data from a group is made available to other groups when the simulated time is advanced to the finish time for the group. Proper timing is thus assured without performing the simulation at the pixel level.
Inventors
- 👤 Michael F. Deering
- 👤 Neil Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:26
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
331 words
A method for simulating on a computer an electronic digital circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output vector on each of said output nets in response to an input vector on each of said input nets according to a known processing behavior, said input vector and said output vector comprising an ordered set of data elements transmitted serially on a net, said method comprising: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid data elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of data elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding data elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output vector in response to at least one input vector according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; and (g) determining a component finish time for each component in the group to generate a latest component finish time.
Claim 2
Independent Claim
331 words
A method for simulating on a computer an electronic digital circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output vector on each of said output nets in response to an input vector on each of said input nets according to a known processing behavior, said input vector and said output vector comprising an ordered set of data elements transmitted serially on a net, said method comprising: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid data elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of data elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding data elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output vector in response to at least one input vector according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; and (g) determining a component finish time for each component in the group to generate a latest component finish time.
Claim 3
Dependent Claim
30 words
The method of claim 1, further comprising the step of: calculating delay values for those components having a variable delay to ensure that all reference element input times are equal.
Claim 4
Dependent Claim
32 words
The method of claim 1 in which said circuit is a circuit for processing video image data and said data elements represent picture elements and said vectors represent frames of picture elements.
Claim 5
Dependent Claim
44 words
The method of claim 3 further comprising the steps of: receiving an input image from a camera; digitizing said image to produce a frame of picture element; and displaying on a monitor at least one group output vector as a frame of picture elements.
Claim 6
Dependent Claim
55 words
The method of claim 1 wherein the circuit comprises a plurality of synchronous groups of components, the method further comprising the steps of: repeating all of the steps of claim 1 for each group in the circuit; and reporting at least one of said group output vectors and a latest one of said finish times.
Claim 7
Dependent Claim
39 words
The method of claim 5 further including the step of passing a group output vector from a first group to a second group having a start time later than the latest component finish time generated for said first group.
Claim 8
Independent Claim
440 words
An apparatus for simulating an electronic circuit for processing visual image data, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, the apparatus comprising: a camera; a frame buffer card coupled to said camera; a computer workstation coupled to said frame buffer card for reading and writing to said frame buffer; a monitor coupled to said frame buffer; said workstation being programmed to simulate the circuit in response to an image from said camera, and to cause an output image to be written to said frame buffer and displayed on said monitor, said program comprising: means for: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets; (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that corresponding picture elements will arrive together at components having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group having at least one input net and at least one output net, to generate at least one group output frame; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism, to generate a circuit output frame; and (i) writing the circuit output frame to said frame buffer card for display on said monitor.
Claim 9
Independent Claim
440 words
An apparatus for simulating an electronic circuit for processing visual image data, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, the apparatus comprising: a camera; a frame buffer card coupled to said camera; a computer workstation coupled to said frame buffer card for reading and writing to said frame buffer; a monitor coupled to said frame buffer; said workstation being programmed to simulate the circuit in response to an image from said camera, and to cause an output image to be written to said frame buffer and displayed on said monitor, said program comprising: means for: (a) defining a group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets; (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that corresponding picture elements will arrive together at components having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group having at least one input net and at least one output net, to generate at least one group output frame; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism, to generate a circuit output frame; and (i) writing the circuit output frame to said frame buffer card for display on said monitor.
Claim 10
Dependent Claim
39 words
The apparatus of claim 7, wherein said workstation is further programmed for calculating delay values for those components having variable delays to ensure that all reference element input times are equal at those components having a plurality of inputs.
Claim 11
Independent Claim
368 words
A method for simulating on a computer an electronic digital visual image processing circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, said method comprising: (a) defining a first group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding picture elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism to generate a circuit output frame and a circuit finish time; and (i) storing the circuit output frame.
Claim 12
Independent Claim
368 words
A method for simulating on a computer an electronic digital visual image processing circuit, said circuit comprising a plurality of components and a plurality of nets for connecting said components, at least one of the components being connected to at least one input net and to at least one output net for generating an output frame on each of said output nets in response to an input frame on each of said input nets according to a known processing behavior, said input frame and said output frame comprising an ordered set of picture elements transmitted serially on a net, said method comprising: (a) defining a first group of components which must operate in synchronism; (b) calculating a scaling factor for each input net connected to any component in the group, the scaling factor indicating a rate at which valid picture elements arrive at the input net; (c) calculating a reference element input time for each input net connected to any component in the group, the reference element input time indicating a time at which a predetermined one of the ordered set of picture elements arrives at the input net; (d) for each component connected to a plurality of input nets: (i) comparing the calculated scaling factors for all of the component's input nets; and (ii) comparing the calculated reference element input times for all of the component's input nets; thereby synchronizing the timing of said group by ensuring that all corresponding picture elements will arrive together at each component having a plurality of inputs; (e) generating and storing at least one output frame in response to at least one input frame according to the known processing behavior of a first component in the group; (f) repeating step (e) for each component in the group connected to at least one input net and at least one output net, to generate at least one group output vector; (g) determining a component finish time for each component in the group to generate a latest component finish time; (h) repeating steps (a) thru (g) for each group of components which must operate in synchronism to generate a circuit output frame and a circuit finish time; and (i) storing the circuit output frame.
Claim 13
Dependent Claim
22 words
The method of claim 9 further comprising the steps of: displaying the stored circuit output frame; and reporting a circuit finish time.
Claim 14
Dependent Claim
37 words
The method of claim 9 further comprising the step of: calculating delay values for those components having variable delays to ensure that all reference element input times are equal at those components having a plurality of inputs.
Claim 15
Dependent Claim
27 words
The method of claim 9 wherein the scaling factors calculated by said calculating step comprise a line rate scaling factor and a picture element rate scaling factor.
Claim 16
Dependent Claim
62 words
The method of claim 9 wherein there is a largest frame in a group and the largest frame has a first picture element and the reference element input time is a relative time at which a first virtual picture element arrives at an input net, the first virtual picture element being the first picture element in the largest frame in the group.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |