US4736338A
Expired / Lapsed
US
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Programmable look up system
Assignee: SILICON SILUTIONS Corp A CORP OF CA
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Filing: 1986-10-07
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Granted: 1988-04-05
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Expires: 2006-10-07
Abstract
Abstract A simulation technique for modeling the function of logic elements containing memory is disclosed. The technique uses a table to represent the logical function of the devices that are being simulated.
Inventors
- 👤 Timothy Saxe
- 👤 Daniel R. Perkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:46
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
218 words
A system for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an address generator that takes as input a set of input values, a set of state values and an element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs, state and element type that is mapped into that location; one or more state output value arrays or memories, each of which is addressed by the output of the address generator and holds state values that represent the next state that the element should assume and where each location of a state output value array holds the value of the state that the element should assume next given the set of inputs, state and element type that is mapped into that location; and one or more feedback paths by which the outputs of the state output value arrays or memories replace the state values stored in the element.
Claim 2
Independent Claim
218 words
A system for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an address generator that takes as input a set of input values, a set of state values and an element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs, state and element type that is mapped into that location; one or more state output value arrays or memories, each of which is addressed by the output of the address generator and holds state values that represent the next state that the element should assume and where each location of a state output value array holds the value of the state that the element should assume next given the set of inputs, state and element type that is mapped into that location; and one or more feedback paths by which the outputs of the state output value arrays or memories replace the state values stored in the element.
Claim 3
Independent Claim
275 words
A system for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an element type modifier that takes as input an element type and a set of state values and generates a modified element type by mapping combinations of element type and state into the modified element type in such a fashion that the modified element type requires no more bits to represent than the original element type required; an address generator that takes as input a set of input values and a modified element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs, state and element type that is mapped into that location; one or more state output value arrays or memories, each of which is addressed by the output of the address generator and holds state values that represent the next state that the element should assume and where each location of a state output value array holds the value of the state that the element should assume next given the set of inputs, state and element type that is mapped into that location; and one or more feedback paths in the logic simulator by which the outputs of the state output value arrays or memories replace the state values associated with the element.
Claim 4
Independent Claim
275 words
A system for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an element type modifier that takes as input an element type and a set of state values and generates a modified element type by mapping combinations of element type and state into the modified element type in such a fashion that the modified element type requires no more bits to represent than the original element type required; an address generator that takes as input a set of input values and a modified element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs, state and element type that is mapped into that location; one or more state output value arrays or memories, each of which is addressed by the output of the address generator and holds state values that represent the next state that the element should assume and where each location of a state output value array holds the value of the state that the element should assume next given the set of inputs, state and element type that is mapped into that location; and one or more feedback paths in the logic simulator by which the outputs of the state output value arrays or memories replace the state values associated with the element.
Claim 5
Dependent Claim
200 words
A technique for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an address generator that takes as input a set of input values and an element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs and element type that is mapped into that location; a next element type array or memory that is addressed by the output of the address generator and holds element types, where each location of the array holds the element type that is used to represent the next element type that corresponds to the set of inputs and element type that is mapped into that location; and a feedback path in the logic simulator whereby the original element type for the element is replaced with the next element type retrieved from the next element type array.
Claim 6
Dependent Claim
200 words
A technique for defining and evaluating the behavior of a memoried logic element that can be used by a logic simulator and comprising in combination: an address generator that takes as input a set of input values and an element type, and generates an address by mapping each possible combination into an address; one or more output value arrays or memories, each of which is addressed by the output of the address generator and holds logic values that represent the logic value of the output and where each location of an output value array holds the output value that corresponds to the set of inputs and element type that is mapped into that location; a next element type array or memory that is addressed by the output of the address generator and holds element types, where each location of the array holds the element type that is used to represent the next element type that corresponds to the set of inputs and element type that is mapped into that location; and a feedback path in the logic simulator whereby the original element type for the element is replaced with the next element type retrieved from the next element type array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-05 | 1991-10-05 | 1992-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-05 | 1995-10-05 | 1996-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-05 | 1999-10-05 | 2000-04-05 | $7700.00 | Window Closed / Lapsed |