Memory system

Claim 2

A relatively high speed memory system comprised of relatively slow speed electronic memory means, said memory system organized as a planar array of rows and columns of word positions and comprising: (a) address generator means for generating sequences of N addresses to access sequences of N words of data along selected substantially straight paths in any direction across said memory array with each address generated having a set of most significant bits and a set of least significant bits; (b) a plurality of electronic memory means, each of said memory means having address decoder means responsive to a plurality of address bits for selecting a memory element within said memory means and enable means responsive to an enable signal for enabling said memory means; and (c) logic means coupling said address generator means to said electronic memory means, said set of least significant bits being selectively coupled to the enable means of said memory means for selectively enabling at least one of said memory means and said most significant bits being selectively coupled to said address decoder means for addressing a selected memory element within said enabled memory means; wherein (d) N is greater than one and wherein no memory means is selected more than once per sequence of N memory accesses.

Claim 3

The memory system of claim 1 wherein each memory element stores a single bit and wherein said selector means selectively simultaneously enables m of said memory means during each memory access to thereby access m-bits which form an m-bit word.

Claim 4

The memory system of claim 1 wherein said memory means are integrated circuit random access memory chips.

Claim 5

The memory system of claim 3 wherein said enable means is the chip select means of said integrated circuit random access memory chip.

Claim 6

The memory system according to claim 4 wherein said memory chips are 1 by n-bit.

Claim 7

The memory system according to claim 5 wherein said memory chips are 16K memory chips.

Claim 8

The memory system of claim 1 wherein each memory element stores an m-bit word.

Claim 9

The memory system of claim 1 wherein said memory system is operable at approximately N times the maximum operating time of said individual electronic memory means.

Claim 10

A relatively high speed memory system comprised of relatively slow speed electronic memory means, said memory system organized as a planar array of rows and columns of word positions and comprising: (a) address generator means for generating sequences of N addresses to access sequencies of N words of data along any selected substantially straight paths in any direction across said memory array with each address generated having a set of most significant bits and a set of least significant bits; (b) a plurality of electronic memory means, each of said memory means having address decoder means responsive to a plurality of address bits for selecting a memory element within said memory means and enable means responsive to an enable signal for enabling said memory means; and (c) logic means coupling said address generator means to said electronic memory means, said logic means including: (i) first means responsible to each address generated by said address generator means for selectively enabling at least one of said memory means during each memory access with N being greater than one and no memory means being selected more than once per sequence of N memory accesses; and (ii) second means responsive to each address generated by said address generator means for addressing a selected memory element within said enabled memory means.

Claim 11

A relatively high speed memory system comprised of relatively slow speed electronic memory means, said memory system organized as a planar array of rows and columns of word positions and comprising: (a) address generator means for generating sequences of N addresses to access sequencies of N words of data along any selected substantially straight paths in any direction across said memory array with each address generated having a set of most significant bits and a set of least significant bits; (b) a plurality of electronic memory means, each of said memory means having address decoder means responsive to a plurality of address bits for selecting a memory element within said memory means and enable means responsive to an enable signal for enabling said memory means; and (c) logic means coupling said address generator means to said electronic memory means, said logic means including: (i) first means responsible to each address generated by said address generator means for selectively enabling at least one of said memory means during each memory access with N being greater than one and no memory means being selected more than once per sequence of N memory accesses; and (ii) second means responsive to each address generated by said address generator means for addressing a selected memory element within said enabled memory means.

Claim 12

The memory system of claim 9 wherein each memory element stores a single bit and wherein said selector means selectively simultaneously enables m of said memory means during each memory access to thereby access m-bits which form an m-bit word.

Claim 13

The memory system according to claim 9 wherein said set of least significant bits is coupled to said first means for generating said enable signal and said most significant bits are coupled to said second means for addressing said least significant bits of said enabled memory means.

Claim 14

The memory system of claim 9 wherein said memory means are integrated circuit random access memory chips.

Claim 15

The memory system of claim 12 wherein said enable means is the chip select means of said integrated circuit random access memory chip.

Claim 16

The memory system according to claim 13 wherein said memory chips are 1 by n-bit.

Claim 17

The memory system according to claim 14 wherein said memory chips are 16K memory chips.

Claim 18

The memory system of claim 9 wherein each memory element stores an m-bit word.

Claim 19

The memory system according to claim 9 wherein said system is operable at a speed approximately N times the maximum operating speed of said memory means.

Claim 20

A relatively high speed memory system comprised of relatively slow speed electronic memory means, said memory system organized as a planar array of rows and columns of memory modules with each memory module organized as a planar array of rows and columns of word positions and comprising: (a) address generator means for generating sequences of N addresses to access sequences of N words of data along selected substantially straight paths in any direction across said arrays with each address generated having a set of most significant bits and a set of least significant bits; (b) a plurality of electronic memory means, each of said memory means having address decoder means responsive to a plurality of address bits for selecting a memory element within said memory means and enable means responsive to an enable signal for enabling said memory means; and (c) logic means coupling said address generator means to said electronic memory means, said set of least significant bits being selectively coupled to the enable means of said memory means for selectively enabling one of said memory means and said most significant bits being selectively coupled to said address decoder means for addressing a selected memory element within said enabled memory means; wherein (d) each of the memory elements of any given memory means is assigned to a row and column position in a different respective memory module, and wherein N is greater than one and wherein no memory means is selected more than once per sequence of N memory accesses.

Claim 21

A relatively high speed memory system comprised of relatively slow speed electronic memory means, said memory system organized as a planar array of rows and columns of memory modules with each memory module organized as a planar array of rows and columns of word positions and comprising: (a) address generator means for generating sequences of N addresses to access sequences of N words of data along selected substantially straight paths in any direction across said arrays with each address generated having a set of most significant bits and a set of least significant bits; (b) a plurality of electronic memory means, each of said memory means having address decoder means responsive to a plurality of address bits for selecting a memory element within said memory means and enable means responsive to an enable signal for enabling said memory means; and (c) logic means coupling said address generator means to said electronic memory means, said set of least significant bits being selectively coupled to the enable means of said memory means for selectively enabling one of said memory means and said most significant bits being selectively coupled to said address decoder means for addressing a selected memory element within said enabled memory means; wherein (d) each of the memory elements of any given memory means is assigned to a row and column position in a different respective memory module, and wherein N is greater than one and wherein no memory means is selected more than once per sequence of N memory accesses.

Claim 22

The memory system of claim 18 wherein each memory element stores a single bit and wherein m planes of said planar arrays of memory modules, are provided, said logic means selectively simultaneously enabling one of said memory means on each of said m planes during each memory access to thereby simultaneously access m bits which form an m-bit word.

Claim 23

The memory system according to claim 18 wherein said memory means are 1 by n-bit integrated circuit random access memory chips.

Claim 24

The memory system according to claim 20 wherein said memory chips are 16K bit memory chips.

Claim 25

The memory system according to claim 20 wherein said memory system is organized as a planar array of P rows and R columns of memory modules where P and R are integers greater than one and the product of P and R is equal to n.

Claim 26

The memory system according to claim 22 wherein said memory modules are organized as planar arrays of p rows and r columns of word positions where p and r are integers greater than one and the product of p and r is equal to the number of memory means comprising a plane of planar modules of the memory system.

Claim 27

The memory system according to claim 23 wherein p and r are each equal to N.