Computer emulator with three segment microcode memory and two separate microcontrollers for operand derivation and execution phases

Claim 1

A microcoded central processing unit (CPU) for emulating the macroinstructions of a target computer by splitting each macroinstruction into operand address derivation and instruction execution phases, the CPU including a main memory for storing the macroinstructions of the target computer, and an address/data bus for coupling the CPU to the main memory, some of the macroinstructions capable of referencing operand address locations, the CPU comprising: (a) a micromemory having an address space, comprising a plurality of micromemory units including at least a right, a middle, and a left micromemory unit with each memory unit separately addressed and each controlling separate CPU resources, for storing the microcoded instructions; (b) a first microcontroller associated with said right micromemory unit and responsive to the microcode stored therein, for generating the micromemory address of the next microcoded instruction to be output from said right micromemory unit, said first microcontroller associated with the operand address derivation phase of the macroinstruction; (c) a second microcontroller associated with said left micromemory unit and responsive to the microcode unit and responsive to the microcode stored therein, for generating the micromemory address of the next microcoded instruction to be output from said left micromemory unit, (i) said second microcontroller being associated with the execution phase of the macroinctruction, the micromemory address generated by either said first or second microcontroller capable of being used to address each said micromemory unit, including the middle micromemory unit whereby each said microcontroller may obtain control of the CPU resources associated with said middle micromemory unit when those resources are needed to perform the operations for its respective phase, and (ii) said right and left controllers capable of operating concurrently and in parallel during the operand address derivation and execution phases of each macroinstruction; (d) a plurality of address selection units each responsive to the microcode and to the addresses from said microcontrollers, and each addressing an associated one of said plurality of micromemory units, (i) for temporarily storing and outputting to its associated micromemory unit, a micromemory address from a selected one of said microcontroller, and (ii) for generating clocking signals to the CPU resources controlled by the microcode stored in its associated micromemory unit, and (iii) where selected ones of said address selection units are inhibited for a period of time from generating their clocking signals when the microcode from a micromemory unit requests CPU resources controlled by another micromemory unit and those resources are not available for use by the requesting microcode; (e) an op-code mapping means responsive to the macroinstructions, for mapping each macroinstruction into the micromemory address space at the starting addresses of microcoded routines which will control the operand address derivation and instruction execution phases for each macroinstruction; (f) a bus interface means responsive to the microcode, for coupling main memory and the peripherals to the CPU; and (g) first and second processing means respectively associated with said first and second microcontrollers and responsive to said bus interface means and to the microcode, each said processing unit including an arithmetic logic unit for performing logical operations on the digital signals of the CPU, whereby the emulation of the macroinstructions is obtained.