Data processing system having two levels of program control

Claim 2

A data processing system comprising: a. local storage means for storing data and address information to be processed; b. operation means connected to said local storage means for performing controlled operations on information supplied thereto from said local storage means; c. first storage means for storing a plurality of instructions each including an operation code; d. means connected to said local storage means and to said first storage means for supplying address information from said local storage means to said first storage means for selecting instructions therein; e. second storage means for storing a plurality of words; f. means connected to said first storage means and utilizing the operation codes of instructions selected from said first storage means for supplying address information to said second storage means for selecting words therein; and g. control means connected to said second storage means for receiving selected words from said second storage means and connected to said operation means for providing in response to each word control functions to control said system, said control means including means for providing control functions of a first type having a given execution time duration and including means for providing control functions of a second type comprising a plurality of portions presented in a sequence, said portions having execution time durations which in sum equal the time duration of the control functions of the first type.

Claim 3

Apparatus according to claim 1, wherein a source of timing pulses is connected to said control means and wherein said control means comprises: a. register means containing a number of bit positions equal to the number of bits of said control functions of the first type; b. a plurality of shift registers, one for each bit of said portion of said control function of said second type, and each shift register having a number of positions equal to the number of said control function portions which are presented in said sequence; and c. means connecting said source of timing pulses to said register means and to said shift registers in a manner whereby each of said pulses normally is applied to said shift registers and one of said pulses is applied to said register means upon completion of each complete cycle of said shift registers.

Claim 4

Apparatus according to claim 1, wherein said local storage means comprises a plurality of registers and wherein a plurality of paths including buses connect said registers of said local storage means to said operation means in response to functions from said control means and wherein said system further comprises: a. register selecting means connected to said buses and to the registers of said local storage means and including a plurality of registers each associated with a particular one of said buses, said register selecting means connecting said buses to selected registers of said local storage means as determined by quantities placed in said registers of said selecting means; and b. means connected to said control means and to said registers of said register selecting means for providing selected registers with selected quantities as determined by functions provided by said control means.

Claim 5

Apparatus according to claim 1, further including external storage means connected to said local storage means and comprising: a. a plurality of channel registers for coupling input-output equipment to said system; b. channel control means connected to said channel registers for controlling the transmission of information between the inpUt-output equipment and said system; and c. means connecting said control means to said channel control means whereby said channel control means is controlled by particular ones of of said control functions provided by said control means.

Claim 6

Apparatus according to claim 1, wherein said local storage means comprises a plurality of registers and wherein said means for supplying address information to said first storage means comprises: a. means connected to said control means and to said local storage means for selecting a register from a group of registers in said local storage means as determined by a function provided by said control means; b. incrementing means for adding a plurality of quantities to the contents of the register selected from said local storage means and for developing a corresponding plurality of results; and c. means connected to said incrementing means and to said control means for selecting an address quantity from among the plurality of results and the contents of said selected register as determined by a function from said control means and for applying said address quantity to said control storage means.

Claim 7

Apparatus according to claim 5 further including means connected to said control means and to said incrementing means for selecting from among the plurality of results and the contents of said selected register as determined by a function from said control means and for placing the selected quantity in the register selected from said local storage means.

Claim 8

Apparatus according to claim 1, wherein said means for supplying address information to said second storage means comprises: a. priority selection means for selecting the current address of highest priority; and b. means connecting said control means to said selection means whereby said selection means is controlled by particular ones of said control functions provided by said control means.

Claim 9

Apparatus according to claim 1, wherein said local storage means comprises a plurality of registers and wherein said apparatus further comprises: a. means connected to said control means and to said local storage means for selecting a register from a group of registers in said local storage means as determined by a function provided by said control means; b. means connected to said control means for selecting an increment value from a plurality of sources as determined by a function provided by said control means; and c. means connected to said register selecting means and said increment value selecting means for adding a selected increment value to the contents of a selected register and for placing the result in the selected register.

Claim 10

Apparatus according to claim 8 wherein said register selecting means includes means for selecting a register selecting quantity from a plurality of sources as determined by said function provided by said control means.

Claim 11

Apparatus according to claim 1 further including: a. main memory means; b. means connecting said main memory means to said local storage means; c. said connecting means including means for varying the format of instruction words transmitted from said main memory means in accordance with parameters supplied thereto; d. storage means containing said parameters; and e. means connecting said control means to said format varying means and to said storage means for selecting parameters and controlling said format varying means in accordance with function provided by said control means.

Claim 12

Apparatus according to claim 1, further including: a. main memory means; b. means connecting said main memory means to said local storage means; and c. said connecting means including indicating means for providing signals whenever information transmitted from said local storage means is attempted to be stored at an address in said main memory means outside of a predetermined address range.

Claim 15

A method according to claim 12, further including providing a priority schedule of addresses including said address formed from said operation code, and wherein said step of fetching an instruction from said second storage means is performed at an address of the highest priority according to said schedule.

Claim 16

In a microprogram computer having operation means for performing controlled operations on information supplied thereto, the improvement comprising: a. a vertically structured control memory containing a plurality of vertical microinstructions each having an operation code field and supporting parameter fields, the operation code field of each microinstruction being coded to select a set of control functions stored in the computer whereby said microinstructions comprise a microprogram for controlling the computer at a first level of program storage, the supporting parameter fields serving as immediate selection values or operands for the microinstructions; b. means for fetching selected microinstructions from said control memory; c. a horizontally structured memory containing a plurality of horizontal words, each word containing a number of bits which is at least a binary order of magnitude greater than the number of bits in each microinstruction contained in said control memory, the bits of each of said horizontal words serving to provide control signals to hardware components of said computer, there being at least one horizontal word corresponding to each microinstruction contained in said control memory for providing an instruction set for executing the selected microinstruction whereby said horizontal words comprise a program for controlling the computer at a second level of program storage; d. register means connected to the output of said control memory for receiving each microinstruction fetched from said control memory, said register means having a portion for said operation code field and a portion for said supporting parameter fields; e. means connected to said portion of said register means for said operation code field and to said horizontally structured memory for fetching words from said horizontally structured memory in accordance with the operation codes of microinstructions fetched from said control memory; f. means connected to the output of said horizontally structured memory and to said operation means for gating the words selected from said memory in a manner such that the bits in said words provide control signals to the hardware components of said computer for executing machine instructions for said computer according to said microprogram in said control memory under vertical control wherein the operation codes of said microinstructions specify a set of control microinstructions through said program in said horizontally structured memory which executes said microinstructions; and g. means connected to the portion of said register means for said supporting parameter fields and to said gating means and to said operation means for controlling the utilization of said fields as determined by said control signals.

Claim 17

In a microprogram computer having operation means for performing controlled operations on information supplied thereto, the improvement comprising: a. a vertically structured control memory containing a plurality of vertical microinstructions each having an operation code field and supporting parameter fields, the operation code field of each microinstruction being coded to select a set of control functions stored in the computer whereby said microinstructions comprise a microprogram for controlling the computer at a first level of program storage, the supporting parameter fields serving as immediate selection values or operands for the microinstructions; b. means for fetching selected microinstructions from said control memory; c. a horizontally structured memory containing a plurality of horizontal words, each word containing a number of bits which is at least a binary order of magnitude greater than the number of bits in each microinstruction contained in said control memory, the bits of each of said horizontal words serving to provide control signals to hardware components of said computer, there being at least one horizontal word corresponding to each microinstruction contained in said control memory for providing an instruction set for executing the selected microinstruction whereby said horizontal words comprise a program for controlling the computer at a second level of program storage; d. register means connected to the output of said control memory for receiving each microinstruction fetched from said control memory, said register means having a portion for said operation code field and a portion for said supporting parameter fields; e. means connected to said portion of said register means for said operation code field and to said horizontally structured memory for fetching words from said horizontally structured memory in accordance with the operation codes of microinstructions fetched from said control memory; f. means connected to the output of said horizontally structured memory and to said operation means for gating the words selected from said memory in a manner such that the bits in said words provide control signals to the hardware components of said computer for executing machine instructions for said computer according to said microprogram in said control memory under vertical control wherein the operation codes of said microinstructions specify a set of control microinstructions through said program in said horizontally structured memory which executes said microinstructions; and g. means connected to the portion of said register means for said supporting parameter fields and to said gating means and to said operation means for controlling the utilization of said fields as determined by said control signals.

Claim 18

Apparatus according to claim 14, wherein said means connected to the output of said horizontally structured memory comprises: a. means for providing control signals of a first type having a given execution time duration; and b. means for providing control signals of a second type comprising a plurality of signals presented in a sequence, said signals having execution time durations which in sum equal the time duration of the control signals of the first type.

Claim 19

Apparatus according to claim 14, wherein said means connected to the output of said horizontally structured memory comprises: a. storage register means into which a portion of the bits of a selected word are placed to provide control signals of a first type; b. shift register means into which the remaining bits of the selected word are placed to provide control signals of a second type; and c. timing means connected to said storage register means and to said shift register means whereby said control signals of the second type are generated in a sequence while said control signals of the first type are generated and held constant.