Method for the testing of electrically programmable memory cells, and corresponding integrated circuit

Claim 3

A testing method according to claim 1, wherein the read voltage produced from an external source voltage, takes different values and wherein the current is measured for said different values, determining a curve of the current as a function of the read voltage.

Claim 4

A testing method according claim 1 or claim 2, wherein the memory is organized in n lines of m words of p bits, the data corresponding to each memory word being capable of being read or recorded from p data input/output pads, wherein the test comprises an operation for the selection of one data bit from among p, said selection being done by the application of a logic signal of a first level to one of the data input/output pads and a second level, complementary to the first level, to all the other data input/output pads.

Claim 5

A testing method according claim 1 or claim 2, wherein a specific signal is applied to at least one external terminal of the integrated circuit to indicate that the system is in testing mode.

Claim 6

A testing method according claim 1 or claim 2, wherein no specific signal indicating that the system is in testing mode is applied, and wherein the integrated circuit includes a mean to detect the presence at the programming terminal of a voltage ranging between two specified voltages levels which are far below that of the programming voltage.

Claim 7

An electrically programmable memory integrated circuit comprising a network of memory cells which can be addressed in reading and programming by word lines, the state of the cells being capable of being read or recorded from bit lines, and a programming terminal being provided to receive and apply, to a bit line, a programming voltage which is higher than voltages applied in reading mode a read voltage is applied to a word line and a test voltage is applied to the bit lines, said circuit comprising a first logic circuit and a second logic circuit receiving both a reading mode signal, a programming mode signal and a testing mode signal, said first logic circuit controlling the application on the word line of either the voltage present at the programming terminal when the memory is in programming mode, or the read voltage when the memory is in reading or testing mode, said second logic circuit connecting a bit line to the programming terminal when the memory is in testing or programming mode.

Claim 8

An electrically programmable memory integrated circuit comprising a network of memory cells which can be addressed in reading and programming by word lines, the state of the cells being capable of being read or recorded from bit lines, and a programming terminal being provided to receive and apply, to a bit line, a programming voltage which is higher than voltages applied in reading mode a read voltage is applied to a word line and a test voltage is applied to the bit lines, said circuit comprising a first logic circuit and a second logic circuit receiving both a reading mode signal, a programming mode signal and a testing mode signal, said first logic circuit controlling the application on the word line of either the voltage present at the programming terminal when the memory is in programming mode, or the read voltage when the memory is in reading or testing mode, said second logic circuit connecting a bit line to the programming terminal when the memory is in testing or programming mode.

Claim 9

A circuit according to claim 6, wherein, in testing mode, the second logic circuit inhibits a read amplifier, connected between the bit line and a data input/output pad.

Claim 10

A circuit according to claim 6 or claim 7, comprising a testing mode terminal to receive a testing mode signal.

Claim 11

A circuit according to claim 6 or claim 7, comprising a circuit for the detection of voltage levels, giving a testing mode signal when the voltage present at the programming terminal ranges between two specified levels which are considerably below that of the programming voltage.