Control circuit for disabling or enabling the provision of redundancy

Claim 2

A logic circuit formed of a high-low-high circuit for activating and deactivating redundant elements comprising: a NOR gate having two inputs and an output, said NOR gate having one input connected to receive a chip select signal and the other input connected to receive a precharging pulse signal; an enable fuse having a first end connected to the output of said NOR gate and a second end connected to a ground potential; an inverter having an input and an output, the input of said inverter being connected to the first end of said enable fuse; a disable fuse having a first end connected to the output of said inverter and a second end connected to an output node; a P-channel MOS transistor having its source connected to a supply potential, its gate connected to the ground potential, and its drain connected to the output node; said output node being in a high logic level when said enable and disable fuses are not blown or opened, said output node being switched to a low logic level when said enable fuse is blown, and said output node being switched back to the high logic level when said enable and disable fuses are blown; and dynamic latch means being coupled to the output node for activating the redundant elements in response to true and complement address signals.

Claim 3

A logic circuit as claimed in claim 1, wherein said enable fuse is formed of a polysilicon material, silicide or metal.

Claim 4

A logic circuit as claimed in claim 2, wherein said enable fuse is blown by a laser cut.

Claim 5

A logic circuit as claimed in claim 1, wherein said disable fuse is formed of a polysilicon material, silicide or metal.

Claim 6

A logic circuit as claimed in claim 4, wherein said disable fuse is blown by a laser cut.

Claim 7

A logic circuit for activating and deactivating redundant elements comprising: (a) high-low-high circuit means including: a NOR gate having two inputs and an output; said NOR gate having one input connected to receive a chip select signal and the other input connected to receive a precharging pulse signal; an enable fuse having a first end connected to the output of said NOR gate and a second end connected to a ground potential; a first inverter having an input and an output, the input of said first inverter being connected to the first end of said enable fuse; a disable fuse having a first end connected to the output of said first inverter and a second end connected to an output node; and a P-channel MOS transistor having its source connected to a supply potential, its gate connected to the ground potential, and its drain connected to the output node; (b) dynamic latch means including: a second P-channel MOS transistor having a source connected to the supply potential, a gate connected to the drain of said first P-channel MOS transistor, and a drain; an N-channel MOS transistor having its drain connected to the drain of said second P-channel MOS transistor, its gate connected to the chip select input signal and its source connected to the ground potential; a second inverter having an input and an output; a third inverter having an input and an output, said third inverter having its input connected to the output of said second inverter and its output connected to the input of said second inverter so as to form a latch, the output of said third inverter being further connected to the drain of said N-channel transistor; a first NAND gate having two inputs and an output, said first NAND gate having its first input connected to the drain of said N-channel transistor and its second input connected to a true address signal; a fourth inverter having an input and an output, the input of said fourth inverter being connected to the output of said first NAND gate and the output of said fourth inverter being connected to a redundant element control line in a right plane; a second NAND gate having two inputs and an output, said second NAND gate having its first input connected to the drain of the N-channel transistor and its second input connected to a complement address signal; and a fifth inverter having an input and an output, the input of said fifth inverter being connected to the output of said second NAND gate and the output of said fifth inverter being connected to a redundant element control line in a left plane.

Claim 8

A logic circuit for activating and deactivating redundant elements comprising: (a) high-low-high circuit means including: a NOR gate having two inputs and an output; said NOR gate having one input connected to receive a chip select signal and the other input connected to receive a precharging pulse signal; an enable fuse having a first end connected to the output of said NOR gate and a second end connected to a ground potential; a first inverter having an input and an output, the input of said first inverter being connected to the first end of said enable fuse; a disable fuse having a first end connected to the output of said first inverter and a second end connected to an output node; and a P-channel MOS transistor having its source connected to a supply potential, its gate connected to the ground potential, and its drain connected to the output node; (b) dynamic latch means including: a second P-channel MOS transistor having a source connected to the supply potential, a gate connected to the drain of said first P-channel MOS transistor, and a drain; an N-channel MOS transistor having its drain connected to the drain of said second P-channel MOS transistor, its gate connected to the chip select input signal and its source connected to the ground potential; a second inverter having an input and an output; a third inverter having an input and an output, said third inverter having its input connected to the output of said second inverter and its output connected to the input of said second inverter so as to form a latch, the output of said third inverter being further connected to the drain of said N-channel transistor; a first NAND gate having two inputs and an output, said first NAND gate having its first input connected to the drain of said N-channel transistor and its second input connected to a true address signal; a fourth inverter having an input and an output, the input of said fourth inverter being connected to the output of said first NAND gate and the output of said fourth inverter being connected to a redundant element control line in a right plane; a second NAND gate having two inputs and an output, said second NAND gate having its first input connected to the drain of the N-channel transistor and its second input connected to a complement address signal; and a fifth inverter having an input and an output, the input of said fifth inverter being connected to the output of said second NAND gate and the output of said fifth inverter being connected to a redundant element control line in a left plane.

Claim 9

A logic circuit as claimed in claim 6, wherein said enable fuse is formed of a polysilicon material, silicide or metal.

Claim 10

A logic circuit as claimed in claim 7, wherein said enable fuse is blown by a laser cut.

Claim 11

A logic circuit as claimed in claim 6, wherein said disable fuse is formed of a polysilicon material, silicide or metal.

Claim 12

A logic circuit as claimed in claim 9, wherein said disable fuse is blown by a laser cut.

Claim 13

A logic circuit as claimed in claim 6, wherein said redundant element control line in the right plane is at a high logic level when said enable fuse is blown and the true address signal is at a high logic level.

Claim 14

A logic circuit as claimed in claim 6, wherein said redundant element control line in the left plane is at a high potential when said enable fuse is blown and said complement address signal is at a high logic level.