EP0055906A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-12-16
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Granted: —
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Expires: 2001-12-16
Abstract
Abstract A semiconductor memory device comprises a plurality of memory cell transistors (Cio -Cin) each of which is disposed at an intersection of a word line (Wi) and a bit line (Bo - Bn) and each of which has a control gate connected to one of the word lines and a floating gate which stores electrons. A first power supply input (Vcc) receives a usual operating voltage, and a second power supply input (Vpp) receives a high voltage for programming the memory device. The device further comprises a circuit (047, Q48) which connects the second power supply input to one or more selected word lines (Wi) when measurement of the threshold potential (Vth) of the memory cell transistors is to be carried out, the first power supply input voltage being maintained constant, and the potential of the second power supply input (Vpp) being changed to effect the measurement of the threshold potential.
Inventors
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 15:43
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/50004; G06; G06F; G06F2201/00; G06F2201/81; G11C16/00; G11C16/02; G11C16/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
172 words
A semiconductor memory device, comprising a plurality of word lines (Wi); a plurality of bit lines (Bo -- Bn); a plurality of memory cell transistors (Cio ---Cin) each of which is disposed at an intersection of the word lines and the bit lines and each of which comprises a control gate connected to one of the word lines and a floating gate which stores electrons; a first power supply input (Vcc) which receives a usual operating voltage; and a second power supply input (Vpp) which receives a high voltage used for programming the memory device; characterised in that the semiconductor memory device further comprises a circuit (Q47,Q48) which connects the second power supply input to one or more selected word lines (Wi) when measurement of the threshold potential (Vth) of the memory cell transistors is effected, the first power supply input being connected to the usual operating voltage having a constant potential (Vcc), and the potential of the second power supply input (Vpp) being changed, thereby effecting measurement of the threshold potential.
Claim 2
Dependent Claim
172 words
A semiconductor memory device, comprising a plurality of word lines (Wi); a plurality of bit lines (Bo -- Bn); a plurality of memory cell transistors (Cio ---Cin) each of which is disposed at an intersection of the word lines and the bit lines and each of which comprises a control gate connected to one of the word lines and a floating gate which stores electrons; a first power supply input (Vcc) which receives a usual operating voltage; and a second power supply input (Vpp) which receives a high voltage used for programming the memory device; characterised in that the semiconductor memory device further comprises a circuit (Q47,Q48) which connects the second power supply input to one or more selected word lines (Wi) when measurement of the threshold potential (Vth) of the memory cell transistors is effected, the first power supply input being connected to the usual operating voltage having a constant potential (Vcc), and the potential of the second power supply input (Vpp) being changed, thereby effecting measurement of the threshold potential.
Claim 3
Dependent Claim
55 words
A memory device as claimed in Claim 1, characterised in that the threshold potential (Vth) is measured in a test mode which is the same as a read-out mode except that the one or more selected word lines (Wi) are connected to the second power supply input (Vpp) and are disconnected from row decoders (RD).
Claim 4
Dependent Claim
79 words
A memory device as claimed in Claim 1 or Claim 2, characterised by first switching transistors (Q47,Q48) each connected between the second power input (Vpp) and each of the word lines (Wi); second switching transistors (Q46) each connected between an output of each row decoder (RD) and a corresponding word line, the threshold potential of one or more memory cells being measured by turning on the first transistors and turning off the second transistors connected to selected word lines.
Claim 5
Dependent Claim
88 words
A memory device as claimed in Claim 3, characterised by a switching signal generator (SSG) which supplies control signals to the first and second switching.transistors (Q46, Q47, Q48) so as to turn on the first switching transistor and turn off the second switching transistor of the row decoder (RD) connected to a selected word line (Wi), when the switching signal generator receives an input signal having a third potential level (AD5) which is different from the potential level of a usual logic signal of the semiconductor memory device.
Claim 6
Dependent Claim
50 words
A memory device as claimed in any preceding claim, characterised by a selecting circuit (CD, RD) which can select a plurality of word lines and/or bit lines at the same time, for measurement of the minimum or maximum value of the threshold potential (Vth) of a plurality of memory cells.
Claim 7
Dependent Claim
68 words
A memory device as claimed in Claim 5, characterised in that the selecting circuit (CD, RD) comprises address buffers (BUF) each of which comprises a non-inverting output (a5) and an inverting output ( a5 ) and can provide output signals having the same potential level from both the non-inverting output and the inverting output in a test mode, thereby selecting a plurality of word lines and/or bit lines.
Claim 8
Dependent Claim
37 words
A device as claimed in Claim 6, characterised in that each address buffer (.BUF) comprises a circuit which cuts off or decreases a current flowing into the address buffer when a powerdown signal (PD2) is applied thereto.
Claim 9
Dependent Claim
50 words
A memory device as claimed in Claim 7, characterised by a powerdown signal generator (PSG) which supplies the powerdown signal (PD2) to the address buffers (BUF) when an input signal having a third potential level (AD5) which is different from the potential level of usual logic signals is applied thereto.
References Cited (Backward Citations)
No citation records indexed.
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