Testable variable-threshold non-volatile semiconductor memory

Claim 1

A semiconductor memory, comprising: a plurality of variable-threshold nonvolatile semiconductor memory transistors arranged in rows and columns, each said memory transistor comprising a source, a drain, and a gate, said gate being a floating gate injectable with electrons and being dischargeable, wherein gates of all transistors in any of said rows are connected to a corresponding word line, drains of all transistors in any of said columns are connected to a corresponding bit line, one of said word lines being selected by a row selection signal being at a first potential, the remaining word lines being non-selected by row selection signals being at a second potential; a plurality of column selection transistors each having a source connected to a respective one of said bit lines and a gate connected to a respective one of a plurality of column selection lines carrying column selection signals; a row decoder and a column decoder receiving address signals for selecting one of said plurality of memory transistors and providing respectively said row selection signals and column selection signals; a sense amplifier having an input connected to drains of all said column selection transistors and providing a sense output for reading said selected one of said memory transistors; and means for selectively applying a third potential to the gates of all of said memory transistors in at least one of said rows, said third potential being between said first potential and said second potential, wherein said sense amplifier detects whether, when said third potential is applied, a drain current flowing through a respective one of said bit lines exceeds a sense current corresponding to said sense output.

Claim 9

A method of testing an array of variable-threshold nonvolatile semiconductor memory transistors, arranged in rows and columns, a drain of each said memory transistor being connected to a bit line associated with a row, a floating gate of each said memory transistor being connected to a word line associated with a column and being selectable by a selection signal at a first potential and being nonselectable by a selection signal at a second potential, said floating gate being injectable with electrons and being dischargeable, said method comprising the steps of: applying a testing signal at a third potential between said first and second potentials to at least one of said word lines; and sensing a drain current, caused by said applying step, into at least one of said bit lines to detect whether said drain current exceeds a sense circuit output by a sense amplifier having a drain connected to a plurality of column selection transistors.

Claim 10

A method of testing an array of variable-threshold nonvolatile semiconductor memory transistors, arranged in rows and columns, a drain of each said memory transistor being connected to a bit line associated with a row, a floating gate of each said memory transistor being connected to a word line associated with a column and being selectable by a selection signal at a first potential and being nonselectable by a selection signal at a second potential, said floating gate being injectable with electrons and being dischargeable, said method comprising the steps of: applying a testing signal at a third potential between said first and second potentials to at least one of said word lines; and sensing a drain current, caused by said applying step, into at least one of said bit lines to detect whether said drain current exceeds a sense circuit output by a sense amplifier having a drain connected to a plurality of column selection transistors.