CMOS memory margining control circuit for a nonvolatile memory

Claim 1

A control circuit for testing the memory margin and the read reference potential of nonvolatile memory cells resident on a substrate having complimentary MOS devices, comprising: wells of first impurity type having formed therein field effect devices of second impurity type, the substrate itself being of second impurity type; means for generating a reference potential on the substrate; means for selectively connecting the reference potential to gate electrodes of selected memory cells in time correspondence with a connection of selected wells for the selected memory cells to a first substrate node providing a first potential; means for enabling the measurement of the reference potential at a second substrate node responsive to a control signal connected through a third substrate node; and means responsive to a memory margining test mode enabling signal on a fourth substrate node for selectively enabling the measurement of memory cell threshold potentials of a first polarity type, corresponding to a first binary state stored in a cell, by connecting a first well bias potential through the third substrate node to selected wells, and by connecting a margin testing potential through the second substrate node to the gate electrodes of selected memory cells, and for selectively enabling the measurement of memory cell threshold potentials of a second polarity type, corresponding to a second binary state stored in a cell, by connecting a second well bias potential through the third substrate node to selected wells, and by connecting a margin testing potential through the second substrate node to the gate electrodes of selected memory cells.