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US4418403A
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Semiconductor memory cell margin test circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1981-02-02
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Granted: 1983-11-29
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Expires: 2001-02-02
Abstract
Abstract A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V cc *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V cc *) is the semiconductor memory circuit main supply source (V cc ) in normal operation but can be forced to a different voltage during the margin test.
Inventors
- 👤 James E. O'Toole
- 👤 Robert J. Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
97 words
A margin testing circuit for a semiconductor memory circuit having a plurality of memory cells, the memory cells being arranged in rows and those memory cells along one row being connected to a word signal line and the semiconductor memory circuit operating at a supply voltage, comprising: means interconnected to a word signal line for varying the voltage applied to a word signal line without varying the supply voltage to test for proper functioning of the memory cells along a row of the semiconductor memory circuit while operating with reduced voltage on the selected word signal line.
Claim 2
Dependent Claim
97 words
A margin testing circuit for a semiconductor memory circuit having a plurality of memory cells, the memory cells being arranged in rows and those memory cells along one row being connected to a word signal line and the semiconductor memory circuit operating at a supply voltage, comprising: means interconnected to a word signal line for varying the voltage applied to a word signal line without varying the supply voltage to test for proper functioning of the memory cells along a row of the semiconductor memory circuit while operating with reduced voltage on the selected word signal line.
Claim 3
Dependent Claim
68 words
The margin testing circuit of claim 1 wherein said means for varying the voltage applied to the word signal lines includes: a voltage supply source; drive means interconnected to said voltage supply source and to the word signal line for driving the word signal line to a voltage dependent on said voltage supply source; and control means for controlling the voltage level supplied to said voltage supply source.
Claim 4
Dependent Claim
117 words
In a semiconductor memory circuit fabricated on a semiconductor substrate, having a plurality of memory cells wherein memory cells are connected to a word signal line, the semiconductor memory circuit having peripheral circuitry and operating from a supply voltage source, a margin test circuit comprising: drive means interconnected to the supply voltage source and to the word line for driving the word line; and control means interconnected to the supply voltage source and to said drive means for controlling the voltage level supplied from the supply voltage source to said drive means to thereby change the voltage level applied to the word signal line while maintaining the semiconductor memory circuit peripheral circuitry at the supply voltage source.
Claim 5
Dependent Claim
117 words
In a semiconductor memory circuit fabricated on a semiconductor substrate, having a plurality of memory cells wherein memory cells are connected to a word signal line, the semiconductor memory circuit having peripheral circuitry and operating from a supply voltage source, a margin test circuit comprising: drive means interconnected to the supply voltage source and to the word line for driving the word line; and control means interconnected to the supply voltage source and to said drive means for controlling the voltage level supplied from the supply voltage source to said drive means to thereby change the voltage level applied to the word signal line while maintaining the semiconductor memory circuit peripheral circuitry at the supply voltage source.
Claim 6
Dependent Claim
17 words
The margin test circuit of claim 3 wherein said control means is external of said semiconductor substrate.
Claim 7
Independent Claim
53 words
A method for separating memory cells of a semiconductor memory circuit having acceptable operating margins from memory cells having unacceptable operating margins comprising the steps of: testing the semiconductor memory circuit with a selected word signal line operating at a reduced voltage; and operating the semiconductor memory circuit peripheral circuitry at normal voltage.
Claim 8
Independent Claim
53 words
A method for separating memory cells of a semiconductor memory circuit having acceptable operating margins from memory cells having unacceptable operating margins comprising the steps of: testing the semiconductor memory circuit with a selected word signal line operating at a reduced voltage; and operating the semiconductor memory circuit peripheral circuitry at normal voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |