Method of testing IC memories

Claim 1

A method of testing a memory comprising a memory cell array, a peripheral circuit including a decoder circuit, a driver circuit and an output circuit, and a common operation power supply voltage for supplying a common power-supply voltage to both the memory cell array and the peripheral circuit, said method comprising the steps of: (a) storing predetermined initially written data into the memory as stored data at a normal common operation power-supply voltage, and reading and confirming whether the initially written data agrees with the stored data; (b) lowering the common operation power-supply voltage when the stored data is in agreement with the initially written data; (c) returning the common operation power-supply voltage to said normal common operation power-supply voltage after a predetermined period of time; (d) confirming whether the stored data is in agreement with the initially written data; and (e) repeating steps (b)-(d) at still lower common operation power-supply voltages until a minimum-operation power-supply voltage which is capable of holding the stored data in agreement with the initially written data is determined.

Claim 2

A method of testing a memory comprising a memory cell array, a peripheral circuit including a decoder circuit, a driver circuit and an output circuit, and a common operation power supply voltage for supplying a common power-supply voltage to both the memory cell array and the peripheral circuit, said method comprising the steps of: (a) storing predetermined initially written data into the memory as stored data at a normal common operation power-supply voltage, and reading and confirming whether the initially written data agrees with the stored data; (b) lowering the common operation power-supply voltage when the stored data is in agreement with the initially written data; (c) returning the common operation power-supply voltage to said normal common operation power-supply voltage after a predetermined period of time; (d) confirming whether the stored data is in agreement with the initially written data; and (e) repeating steps (b)-(d) at still lower common operation power-supply voltages until a minimum-operation power-supply voltage which is capable of holding the stored data in agreement with the initially written data is determined.

Claim 5

A method of testing a memory, comprising the steps of: (a) writing data into memory cells of the memory at a normal operating voltage; (b) lowering the operating voltage to a test voltage for a predetermined period of time; (c) returning the operating voltage to normal; (d) reading out the data and comparing it to the written data after the operating voltage is returned to normal; (e) repeating steps (b)-(d) in cycles using successively lower values for the test voltage until the data written into the memory cells does not match the data read out; and (f) designating, as a minimum memory cell data holding voltage limit, the test voltage value used in the cycle immediately before the data written into the memory cells does not match the data read out.

Claim 6

A method of testing a memory, comprising the steps of: (a) writing data into memory cells of the memory at a normal operating voltage; (b) lowering the operating voltage to a test voltage for a predetermined period of time; (c) returning the operating voltage to normal; (d) reading out the data and comparing it to the written data after the operating voltage is returned to normal; (e) repeating steps (b)-(d) in cycles using successively lower values for the test voltage until the data written into the memory cells does not match the data read out; and (f) designating, as a minimum memory cell data holding voltage limit, the test voltage value used in the cycle immediately before the data written into the memory cells does not match the data read out.