Method and apparatus for testing high circuit density devices

Claim 2

An electronic test system for testing high density logic networks having n input terminals and m output terminals, where n and m are integer numbers respectively greater than ten, said system employing test patterns under control of a system test program, where each test pattern includes a plurality of test steps and each test step includes n discrete electrical manifestations of logical ones and/or logical zeros, said test system comprising: a system controller operative under control of said test program for providing test pattern data, including said n discrete electrical manifestations, during each of said test steps, said system controller including storage means for storing Test Patterns, Expected Test Result Data and Pass/Fail Test Data; first circuit means responsive to said system controller for accepting, during each test step, said n discrete electrical manifestations of logical ones and/or logical zeros, second circuit means responsive to said first circuit means for randomly rendering either a first or a second discrete electrical manifestation representative of each of said logical ones and/or either a first or a second discrete electrical manifestation representative of each of said logical zeros; third circuit means coupled to said second circuit means and said n input terminals of the high density logic network under test for impressing on each of said n input terminals either said first or second discrete electrical manifestation of a logical one where said test pattern step designates a logical one be applied to said terminal, or said first or second discrete electrical manifestation of a logical zero where said test pattern step designates a logical zero be applied to said terminal; fourth means coupled to said m output terminals of said high density logic network under test and to said system controller, for accepting and comparing during each test step the output of said high density logic network and the Expected Results Data from said System Controller, said fourth means rendering to said system controller Pass/Fail Test Data relative to the high density logic network under test.

Claim 3

An electronic test system for testing large scale integration devices having n input pins and m output pins, where n and m are respectively integer numbers greater than 10 and less than 3,000, and n and m bear no fixed mathematical relationship one to the other, said system employing test patterns under control of a system test program, each test pattern including a plurality of test steps, each test step including at least n discrete electrical manifestations of logical ones and logical zeros, said n discrete electrical manifestations of logical ones and logical zeros of each said test step representing a portion of the truth table for the large Scale Integration device under test, said electronic test system comprising: a system controller for controlling said electronic test system, said system controller including storage means for storing data including at least one test program having at least one test pattern including a plurality of test steps, said system controller being operative under and in response to said test program to sequentially present each successive step of said test pattern, said system controller being further operative and responsive to said test program to provide, in timed relationship with each step of said test pattern, a system Synch signal, and an Expected Results data signal, said system controller being further operative and responsive to said test program to accept and store, in timed relationship with each step of said test pattern, A Pass/Fail Data signal; n electronic channel means, each said channel means adapted to receive one of said n discrete electrical manifestations, each said channel means coupled to a discrete one of said n input terminals of said large scale integration device under test; System timing means adapted to receive said System synch signals and provide respectively in timed relationship to each said system synch signal a Random Pulse Enable Signal, a Drive Command Signal, and a Sample Data Command Signal; each of said channel means including Decode Logic means for accepting said one of said n discrete electrical manifestations, each of said channel means including a free running random pulse generator having an output, and an And circuit having first and second inputs and an output, said first input of said And circuit connected to said System Timing means for receiving said Random Pulse Enable Signal, said second input of said And circuit connected to said output of said Random Pulse generator and said output of said And circuit connected to said Decode Logic means, said Decode Logic means of each of said n channels including a first bistable device, a second bistable device, a third bistable device and And circuit means, said first bistable device having an output and being adapted to receive, via siad And circuit, and under control of said Random Pulse Enable Signal, a random number of pulses, said first bistable device assuming in response to said pulses a first steady-state condition or a second steady-state condition, said first steady-state condition of said first bistable device being manifested at said output of said first bistable device by a first electrical potential and said second steady-state condition of said first bistable device being manifested at said output of said bistable device by a second electrical potential, said first electrical potential being greater in magnitude than said second electrical potential, said second bistable device having a first input adapted to receive one of said n discrete electrical manifestations, said second bistabale device having a second input adapted to receive said Drive Command Signal, said second bistable device having first and second outputs respectively coupled to said And circuit means, said third bistable device having a first input adapted to receive the output of said first bistable device, said third bistable device having a second input adapted to receive said Drive Command Signal, said third bistable device having first and second outputs respectively coupled to said And circuit means; said And circuit means having four discrete output lines only one of which is activated during each of said test pattern steps in response to said first and second outputs from said second and third bistable devices, said four discrete output lines respectively issuing electrically the following commands, Hi-One Select, Lo-One Select, Hi-Zero Select, and Lo-Zero Select, each in response to a particular steady-state condition of said second and third bistable devices; discrete input driver means included within each of said n electronic channel means, each said driver means connected to said four dicrete output lines of said And circuit means, each said input driver means having an output for electrically manifesting either a logical one at either a MOST Positive UP Level or a Least Positive UP Level, or a logical zero at either a Least Negative Down Level or a MOST Negative Down Level during each test pattern step, and respectively, in response to one of said electrically manifested commands from said Decode logic means; means coupling the output of each of said n driver means to a discrete one of said n input terminals of a Large Scale Integration Device under test; comparator means connected to said m output terminals of said Large Scale Integration Device, and adapted to receive during each test pattern step said Expected Results Data Signal and said Sample Data Command signal, said comparator means rendering a Pass/Fail Data signal based on a comparison of output data from said device under test and said Expected Results Data Signal, whereby each said Large Scale Integration device under test has impressed on each of said n input terminals, during each test pattern step, an electrical manifestation of a logical one or zero as directed by said test pattern step, where said electrical manifestations of said logical ones are randomly at either said Most Positive UP Level or said Least Positive UP Level, and said electrical manifestations of said logical zeros are randomly at either said Least Negative Down Level or said Most Negative Down Level, and a determination is made as to the merit of the device under test based on the output therefrom.

Claim 4

An electronic test system for testing large scale integration devices having n input pins and m output pins, where n and m are respectively integer numbers greater than 10 and less than 3,000, and n and m bear no fixed mathematical relationship one to the other, said system employing test patterns under control of a system test program, each test pattern including a plurality of test steps, each test step including at least n discrete electrical manifestations of logical ones and logical zeros, said n discrete electrical manifestations of logical ones and logical zeros of each said test step representing a portion of the truth table for the large Scale Integration device under test, said electronic test system comprising: a system controller for controlling said electronic test system, said system controller including storage means for storing data including at least one test program having at least one test pattern including a plurality of test steps, said system controller being operative under and in response to said test program to sequentially present each successive step of said test pattern, said system controller being further operative and responsive to said test program to provide, in timed relationship with each step of said test pattern, a system Synch signal, and an Expected Results data signal, said system controller being further operative and responsive to said test program to accept and store, in timed relationship with each step of said test pattern, A Pass/Fail Data signal; n electronic channel means, each said channel means adapted to receive one of said n discrete electrical manifestations, each said channel means coupled to a discrete one of said n input terminals of said large scale integration device under test; System timing means adapted to receive said System synch signals and provide respectively in timed relationship to each said system synch signal a Random Pulse Enable Signal, a Drive Command Signal, and a Sample Data Command Signal; each of said channel means including Decode Logic means for accepting said one of said n discrete electrical manifestations, each of said channel means including a free running random pulse generator having an output, and an And circuit having first and second inputs and an output, said first input of said And circuit connected to said System Timing means for receiving said Random Pulse Enable Signal, said second input of said And circuit connected to said output of said Random Pulse generator and said output of said And circuit connected to said Decode Logic means, said Decode Logic means of each of said n channels including a first bistable device, a second bistable device, a third bistable device and And circuit means, said first bistable device having an output and being adapted to receive, via siad And circuit, and under control of said Random Pulse Enable Signal, a random number of pulses, said first bistable device assuming in response to said pulses a first steady-state condition or a second steady-state condition, said first steady-state condition of said first bistable device being manifested at said output of said first bistable device by a first electrical potential and said second steady-state condition of said first bistable device being manifested at said output of said bistable device by a second electrical potential, said first electrical potential being greater in magnitude than said second electrical potential, said second bistable device having a first input adapted to receive one of said n discrete electrical manifestations, said second bistabale device having a second input adapted to receive said Drive Command Signal, said second bistable device having first and second outputs respectively coupled to said And circuit means, said third bistable device having a first input adapted to receive the output of said first bistable device, said third bistable device having a second input adapted to receive said Drive Command Signal, said third bistable device having first and second outputs respectively coupled to said And circuit means; said And circuit means having four discrete output lines only one of which is activated during each of said test pattern steps in response to said first and second outputs from said second and third bistable devices, said four discrete output lines respectively issuing electrically the following commands, Hi-One Select, Lo-One Select, Hi-Zero Select, and Lo-Zero Select, each in response to a particular steady-state condition of said second and third bistable devices; discrete input driver means included within each of said n electronic channel means, each said driver means connected to said four dicrete output lines of said And circuit means, each said input driver means having an output for electrically manifesting either a logical one at either a MOST Positive UP Level or a Least Positive UP Level, or a logical zero at either a Least Negative Down Level or a MOST Negative Down Level during each test pattern step, and respectively, in response to one of said electrically manifested commands from said Decode logic means; means coupling the output of each of said n driver means to a discrete one of said n input terminals of a Large Scale Integration Device under test; comparator means connected to said m output terminals of said Large Scale Integration Device, and adapted to receive during each test pattern step said Expected Results Data Signal and said Sample Data Command signal, said comparator means rendering a Pass/Fail Data signal based on a comparison of output data from said device under test and said Expected Results Data Signal, whereby each said Large Scale Integration device under test has impressed on each of said n input terminals, during each test pattern step, an electrical manifestation of a logical one or zero as directed by said test pattern step, where said electrical manifestations of said logical ones are randomly at either said Most Positive UP Level or said Least Positive UP Level, and said electrical manifestations of said logical zeros are randomly at either said Least Negative Down Level or said Most Negative Down Level, and a determination is made as to the merit of the device under test based on the output therefrom.

Claim 5

An electronic test system, as recited in claim 2, wherein said input driver means includes first, second, third and fourth field effect transistor switch means.

Claim 6

An electronic test system as recited in claim 3, wherein said means coupling the output of each of said n driver means to a discrete one of said n input terminals, comprises Operational Amplifier means.

Claim 7

An electronic test system as recited in claim 4 wherein said comparator means compares the output at each of said m output terminals with the corresponding portion of said Expected Results Data Signal and said Pass/Fail Data Signal electrically manifests the merit or lack of merit of the output electrically manifested at each of said m output terminals.

Claim 8

An electronic test system for testing a Large Scale Integration logic device having n input terminals and m output terminals, where n and m are respectively integer numbers greater than 10 and not exceeding 3,000, said system employing at least one test pattern under control of a system test program, each test pattern including a plurality of test steps, each test step of each test pattern including at least n discrete electrical manifestations, x of said discrete electrical manifestations representing logical ones, n-x of said discrete electrical manifestations representing logical zeros, where x is any integer number from zero through n, said test system comprising: a system controller, said system controller including storage means for storing said test program, said test patterns, Expected Results Data and Pass/Fail Data, said system controller being operative under control of said test program for providing said x discrete electrical manifestations representing logical ones and said n-x discrete electrical manifestations representing logical zeros during each test step of a test pattern, first circuit means connected to said system controller for accepting said x electrical manifestations of a logical one and said n-x electrical manifestations of a logical zero and providing y electrical manifestations of a logical one at a first electrical magnitude, x-y electrical manifestations of a logical one at a second electrical magnitude, z electrical manifestations of a logical zero at a third electrical magnitude, and n-x-z electrical manifestationss of logical zero at a fourth electrical magnitude, where y is an integer in the range of zero through x, z is any integer in the range of zero through n-x and said first, second, third and fourth electrical magnitudes are respectively unequal in magnitude; second means responsive to said first means for impressing each of said electrical manifestations provided by said first means on a discrete predetermined one of said n input terminals of said device under test; comparator means coupled to said m output terminals of said device under test and to said system conTroller, for accepting and comparing during each said test step the output of said device under test and the Expected Result Data from said System Controller and rendering to said System Controller Pass/Fail Test Data relative to the device under test.

Claim 9

An electronic test system for testing a Large Scale Integration logic device having n input terminals and m output terminals, where n and m are respectively integer numbers greater than 10 and not exceeding 3,000, said system employing at least one test pattern under control of a system test program, each test pattern including a plurality of test steps, each test step of each test pattern including at least n discrete electrical manifestations, x of said discrete electrical manifestations representing logical ones, n-x of said discrete electrical manifestations representing logical zeros, where x is any integer number from zero through n, said test system comprising: a system controller, said system controller including storage means for storing said test program, said test patterns, Expected Results Data and Pass/Fail Data, said system controller being operative under control of said test program for providing said x discrete electrical manifestations representing logical ones and said n-x discrete electrical manifestations representing logical zeros during each test step of a test pattern, first circuit means connected to said system controller for accepting said x electrical manifestations of a logical one and said n-x electrical manifestations of a logical zero and providing y electrical manifestations of a logical one at a first electrical magnitude, x-y electrical manifestations of a logical one at a second electrical magnitude, z electrical manifestations of a logical zero at a third electrical magnitude, and n-x-z electrical manifestationss of logical zero at a fourth electrical magnitude, where y is an integer in the range of zero through x, z is any integer in the range of zero through n-x and said first, second, third and fourth electrical magnitudes are respectively unequal in magnitude; second means responsive to said first means for impressing each of said electrical manifestations provided by said first means on a discrete predetermined one of said n input terminals of said device under test; comparator means coupled to said m output terminals of said device under test and to said system conTroller, for accepting and comparing during each said test step the output of said device under test and the Expected Result Data from said System Controller and rendering to said System Controller Pass/Fail Test Data relative to the device under test.

Claim 10

An electronic test system for testing a high circuit density logic device, said logic device having n input terminals and m output terminals, where n and m are respectively integers having a magnitude greater than ten and less than three thousand, said system employing at least one test pattern control of a system test program, each said test pattern including a plurality of test steps, each said test step including n discrete electrical manifestations, t of said discrete electrical manifestations representing logical ones, n-t of said discrete electrical manifestations representing logical zeros, where t is any integer number ranging in value from zero through n, said test system comprising: a system controller, said system controller including storage means for storing said test program, said test pattern, Expected Results Data and Pass/Fail Data, said system controller operative under control of said test program for provding said t discrete electrical manifestations representing logical ones and said n-t discrete electrical manifestations representing logical zeros during each test step of a test pattern; first circuit means connected to said system controller for accepting said t discrete electrical manifestations of a logical one and randomly modifying the electrical manifestation of v of said t discrete electrical manifestations, where v is any integer in the range of zero through t; said second circuit means connected to said system controller for accepting said n-t discrete electrical manifestations of a logical zero and randomly modifying the electrical manifestation of s of said n-t discrete electrical manifestations, where s is any integer in the range of zero through n-t; third circuit means coupled to said first and second circuit means and connected to said n input terminals for impressing said n electrical manifestations received from said first and second circuit means on said n input terminals where each of said n input terminals has an electrical manifestation of either a logical one or logical zero impressed thereon as dictated by the one and zero content of said test step of said test pattern; comparator means coupled to said m output terminals of said device under test and to said system controller, for accepting the output of the device under test and the expected Result Data from said System Controller, and rendering to said System Controller Pass/Fail Test Data pertaining to the device of under test.

Claim 11

An electronic test system for testing a high circuit density logic device, said logic device having n input terminals and m output terminals, where n and m are respectively integers having a magnitude greater than ten and less than three thousand, said system employing at least one test pattern control of a system test program, each said test pattern including a plurality of test steps, each said test step including n discrete electrical manifestations, t of said discrete electrical manifestations representing logical ones, n-t of said discrete electrical manifestations representing logical zeros, where t is any integer number ranging in value from zero through n, said test system comprising: a system controller, said system controller including storage means for storing said test program, said test pattern, Expected Results Data and Pass/Fail Data, said system controller operative under control of said test program for provding said t discrete electrical manifestations representing logical ones and said n-t discrete electrical manifestations representing logical zeros during each test step of a test pattern; first circuit means connected to said system controller for accepting said t discrete electrical manifestations of a logical one and randomly modifying the electrical manifestation of v of said t discrete electrical manifestations, where v is any integer in the range of zero through t; said second circuit means connected to said system controller for accepting said n-t discrete electrical manifestations of a logical zero and randomly modifying the electrical manifestation of s of said n-t discrete electrical manifestations, where s is any integer in the range of zero through n-t; third circuit means coupled to said first and second circuit means and connected to said n input terminals for impressing said n electrical manifestations received from said first and second circuit means on said n input terminals where each of said n input terminals has an electrical manifestation of either a logical one or logical zero impressed thereon as dictated by the one and zero content of said test step of said test pattern; comparator means coupled to said m output terminals of said device under test and to said system controller, for accepting the output of the device under test and the expected Result Data from said System Controller, and rendering to said System Controller Pass/Fail Test Data pertaining to the device of under test.

Claim 12

A test method for testing a Large Scale Integration Logic Device having n input terminals and m output terminals where n and m are respectively any integer number in the range of ten through three thousand, said method comprising the steps of: a. generating t discrete logical one electrical manifestations and s discrete logical zero electrical manifestations, where s and t are respectively integer numbers in the range of zero to 2,000, the sum of s and t being equal to n, and for each step of a test pattern the absolute value of t being dictated by the truth table for the device under test; b. electrically modifying v of said t discrete logical one manifestations, where v is an integer number having any value within the range of zero through t; c. electrically modifying u of said s discrete logical zero manifestations, where u is an integer number having any magnitude within the range of zero through s; d. impressing each of the n electrical manifestations, where said N electrical manifestations consists of said v, t-v, u and s-u electrical manifestations, on a discrete predetermined one of said n input terminals of said device under test; e. comparing the output appearing at said m output terminals, in response to receipt of said n electrical manifestations by said device under test, with a known standard; and, f. rendering an electrical manifestation of the result of said comparison of the output of said device under test and said known standard.

Claim 13

A test method for testing a Large Scale Integration Logic Device having n input terminals and m output terminals where n and m are respectively any integer number in the range of ten through three thousand, said method comprising the steps of: a. generating t discrete logical one electrical manifestations and s discrete logical zero electrical manifestations, where s and t are respectively integer numbers in the range of zero to 2,000, the sum of s and t being equal to n, and for each step of a test pattern the absolute value of t being dictated by the truth table for the device under test; b. electrically modifying v of said t discrete logical one manifestations, where v is an integer number having any value within the range of zero through t; c. electrically modifying u of said s discrete logical zero manifestations, where u is an integer number having any magnitude within the range of zero through s; d. impressing each of the n electrical manifestations, where said N electrical manifestations consists of said v, t-v, u and s-u electrical manifestations, on a discrete predetermined one of said n input terminals of said device under test; e. comparing the output appearing at said m output terminals, in response to receipt of said n electrical manifestations by said device under test, with a known standard; and, f. rendering an electrical manifestation of the result of said comparison of the output of said device under test and said known standard.

Claim 14

The test method as recited in claim 8 further characterized by randomly determining the values of v and u, respectively.

Claim 15

The test method as recited in claim 8 further characterized by employing predetermined values of v and u, respectively, and wherein each of said v discrete logical one electrical manifestation results from the modification of a predetermined one of said t discrete logical one electrical manifestations and each of said u discrete logical zero electrical manifestations results from the modification of a predetrmined one of said s discrete logical zero manifestations.

Claim 16

The test method as recited in claim 8 further characterized by said v discrete logical one electrical manifestations being respectively at a first electrical potential, said t-v discrete logical one electrical manifestations being respectively at a second electrical potential, said u discrete logical zero electrical manifestations being respectively at a third electrical potential, and said s-u discrete logical zero electrical manifestations being respectively at a fourth electrical potential, where said first, second, third and fourth electrical potentials are respectively unequal one to another in mangnitude.

Claim 17

The test method as recited in claim 8 further characterized by said v discrete logical one electrical manifestations being respectively a first electrical potential varying in magnitude in a predetermined manner during a test time period t1, said t-v discrete logical one electrical manifestations being respectively a second electrical potential non-variant in magnitude during said time period t1, said u discrete logical zero electrical manifestations being respectively at a third electrical potential varying in magnitude in a predetermined manner during said time period t1, and said s-u discrete logical zero electrical manifestations being respectively at a fourth electrical potential non-variant in magnitude during said time period t1, where said first, second, third and fourth electrical potentials are respectively unequal, one to one another, in magnitude during said time period t1 and said time period t1 is small portion of a second.

Claim 18

The test method as recited in claim 8 further characterized by said v discrete logical one electrical manifestations being respectiveley at a MOST POSITIVE UP LEVEL electrical potential, said t-v discrete logical one electrical manifestations being respectively at a LEAST POSITIVE UP LEVEL electrical potential, said u discrete logical zero electrical manifestations being respectively at a LEAST NEGATIVE DOWN LEVEL electrical potential, and said s-u discrete logical zero electrical manifestations being respectively at a MOST NEGATIVE DOWN LEVEL electrical potential.

Claim 19

In an electronic test system for testing high circuit density devices, said devices having n input pins and m output pins, where n and m are respectively integer numbers each having any value in the range of 10 through 3,000, said system including: first means for presenting, during each successive time period of a plurality of time periods during the test time for one device, a binary word having n binary bit positions where each bit position has an electrical manifestations denoting the presEnce of either a binary one or a binary zero; a pin driver circuit for each of said n binary bit positions, each said pin driver circuit including second means for electrically manifesting either a Low command or a High command, and each said driver circuit including third means coupled to said first and second means, and adapted to receive said electrical manifestation of either a binary one or a binary zero corresponding a particular bit position of said n binary bit position word, said third means having an output terminal for rendering any one and only one of four possible electric output manifestations, said four possible electrical output manifestations being respectively High one, Low one, High zero, and Low zero, whereby said High one is electrically manifested at said output terminal of said third means in response to receipt of a High command and a binary one by said third means, said Low one is electrically manifested at said output terminal of said third means in response to receipt of a Low command and a binary one by said third means, said High zero is electrically manifested at said output terminal of said third means in response to receipt of a High command and a binary zero by said third means, and said Low zero is electrically manifested at said output terminal of said third means in response to receipt of a Low command and a binary zero by said third means.

Claim 20

In an electronic test system for testing high circuit density devices, said devices having n input pins and m output pins, where n and m are respectively integer numbers each having any value in the range of 10 through 3,000, said system including: first means for presenting, during each successive time period of a plurality of time periods during the test time for one device, a binary word having n binary bit positions where each bit position has an electrical manifestations denoting the presEnce of either a binary one or a binary zero; a pin driver circuit for each of said n binary bit positions, each said pin driver circuit including second means for electrically manifesting either a Low command or a High command, and each said driver circuit including third means coupled to said first and second means, and adapted to receive said electrical manifestation of either a binary one or a binary zero corresponding a particular bit position of said n binary bit position word, said third means having an output terminal for rendering any one and only one of four possible electric output manifestations, said four possible electrical output manifestations being respectively High one, Low one, High zero, and Low zero, whereby said High one is electrically manifested at said output terminal of said third means in response to receipt of a High command and a binary one by said third means, said Low one is electrically manifested at said output terminal of said third means in response to receipt of a Low command and a binary one by said third means, said High zero is electrically manifested at said output terminal of said third means in response to receipt of a High command and a binary zero by said third means, and said Low zero is electrically manifested at said output terminal of said third means in response to receipt of a Low command and a binary zero by said third means.

Claim 21

In an electronic test system as claimed in claim 14 where said second means includes a bistable device having first and second states, whereby said second means electrically manifests a High command when said bistable device is in said first state and said second means electrically manifests said Low command when said bistable device is in said second state.

Claim 22

In an electronic test system as claimed in claim 15 wherein random means is provided for randomly determining the state of said bistable device during each of said successive time periods.

Claim 23

In an electronic test system as claimed in claim 15 wherein additional means is provided for setting said bistable device in either said first state or said second state, as desired, during each of said successive time periods.

Claim 24

In an electronic test system for testing high circuit density devices, said devices having n input pins and m output pins, where n and m are respectively any integer number in the range of 10 through 3,000, said system including: first circuit means for accepting either a first electrical manifestation representative of a logical one, or a second electrical manifestation representative of a logical zero; controllable second circuit means cooperating with said first circuit means for rendering either a third electrical manifestation representative of a logical one, or a fourth electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means; controllable third circuit means cooperating with said first circuit means for rendering either a fifth electrical manifestation representative of a logical zero, or a sixth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation respresentative of a logical zero by said first means; and settable control circuit means for controlling said second controllable circuit means and said third controllable circuit means, whereby under control of said settable control circuit means a logical one will be represented by either a third electrical manifestation, or a fourth electrical manifestation, and a logical zero will be represented by either a fifth electrical manifestation or a sixth electrical manifestation, under control of the setting of said settable control circuit means.

Claim 25

In an electronic test system for testing high circuit density devices, said devices having n input pins and m output pins, where n and m are respectively any integer number in the range of 10 through 3,000, said system including: first circuit means for accepting either a first electrical manifestation representative of a logical one, or a second electrical manifestation representative of a logical zero; controllable second circuit means cooperating with said first circuit means for rendering either a third electrical manifestation representative of a logical one, or a fourth electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means; controllable third circuit means cooperating with said first circuit means for rendering either a fifth electrical manifestation representative of a logical zero, or a sixth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation respresentative of a logical zero by said first means; and settable control circuit means for controlling said second controllable circuit means and said third controllable circuit means, whereby under control of said settable control circuit means a logical one will be represented by either a third electrical manifestation, or a fourth electrical manifestation, and a logical zero will be represented by either a fifth electrical manifestation or a sixth electrical manifestation, under control of the setting of said settable control circuit means.

Claim 26

In an electronic test system as claimed in claim 18 the provision of random means for randomly setting said settable control means in either one of two states, whereby when said settable control means is set to said first state said controllable second circuit means renders said third electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means, and said controllable third circuit means renders said fifth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation representative of a logical zero by said first circuit means, and when said settable control means is set to said second state said controllable second circuit means renders said fourth electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means, and said controllable third circuit means renders said sixth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation representative of a logical zero by said first circuit means.

Claim 27

In an electronic test system as claimed in claim 18 the provision of control means for setting said settable control means in either one of two states, whereby when said settable control means is set to said first state said controllable second circuit means renders said third electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means, and said controllable third circuit means renders said fifth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation representative of a logical zero by said first circuit means, and when said settable control means is set to said second state said controllable second circuit means renders said fourth electrical manifestation representative of a logical one in response to receipt of said first electrical manifestation representative of a logical one by said first circuit means, and said controllable third circuit means renders said sixth electrical manifestation representative of a logical zero in response to receipt of said second electrical manifestation representative of a logical zero by said first circuit means.

Claim 28

In an electronic test system as claimed in claim 20: n electronic channels, each of said n electronic channels including said first circuit means, said controllable second circuit means, said controllable third circuit means, said settable control circuit means and said control means; and n connection means for connecting each of said n electronic channels to a predetermined discrete one of said n input pins, whereby the particular electrical manifestation impressed on each of said n input pins is determined by the particular electrical manifestation impressed on said first circuit means and the status of said control means of the electronic channel connected to said input pin.

Claim 29

In an electronic test system for testing high density logic networks having n input pins and m output pins, where n and m are integer numbers respectively having any value in the range of 10 through 3,000, a pin driver circuit comprising: a first bistable device having an input terminal and an ouput terminal, said first bistable device having a first state and a second state of conductivity and being adapted to electrically manifest at said output a High command representative of said first state and a Low command representative of said second state; a second bistable device having first and second input terminals and first and second ouput terminals, said second bistable device having first and second states of conductivity; a third bistable device having first and second input terminals and first and second output terminals, said third bistable device having first and second states of conductivity; means connecting said output terminal of said first bistable device to said first input terminal of said third bistable device; data source means for impressing on said first input terminal of said second bistable device an electrical manifestation of a logical one, or an electrical manifestation of a logical zero; means connected to said input of said first bistable device for causing said device to assume said first state or said second state, said first bistable device electrically manifesting a High command when in said first state, and electrically manifesting a Low command when in said second state; a source of timing signals connected to said second input terminals of said second and third bistable devices, respectively, whereby in response to a timing signal, said second bistable device will assume its first state in response to a logical one and its second state in response to a logical zero, and said third bistable device will assume its first state in response to said High command and its second state in response to said Low command; a first AND circuit having an output, a first input connected to said first output terminal of said second bistable device, and a second input connected to said first output terminal of said third bistable device, a second AND circuit having an output, a first input connected to said output terminal of said second bistable device and a second input connected to said second output of said third bistable device, a third AND circuit having an output, a first input connected to said second output terminal of said second bistable device and a second input connected to said first output terminal of said third bistable device, and a fourth AND circuit having an output, a first input connected to said second output terminal of said second bistable device, and a second input connected to said second output terminal of said third bistable device, whereby said output of said first AND circuit electrically manifests a High-One Select Command when said second and third bistable devices are respectively in said first state, said output of said second AND circuit electrically manifests a Low-One Select Command when said second bistable device is in said first state and said third bistable device is in said second state, said output of said third AND circuit electrically manifests a High-Zero Select Command when said second bistable device is in said second state and third bistable device is in said first state, and said output of said fourth AND circuit electrically manifests a Low-Zero Select Command when said second bistable device is in said second state, and said third bistable device is in said second state; Operational Amplifier means having an input terminal and an output terminal; first field effect transistor switch means interconnecting said output terminal of said first AND circuit and said input terminal of said Operational Amplifier means, second field effect transistor switch means interconnecting said output terminal of said second AND circuit and said input terminal of said Operational Amplifier means; third field effect transistor switch means interconnecting said output terminal of said third AND circuit and said input terminal of said Operational Amplifier means, and fourth field effect transistor switch means interconnecting said output terminal of said fourth AND circuit and said input terminal of said operational amplifier means, whereby, in response to said High-One Select Command said first field effect transistor switch means is activated and a High logical one electrical manifestation appears at said output terminal of said Operational Amplifier means, in response to said Low-One Select Command, said second field effect transistor switch means is activated and a Low logical one electrical manifestation appears at said output terminal of said Operational Amplifier means, in response to said High Zero Select Command, said third field effect transistor swiTch means is activated and a High logical zero electrical manifestation appears at said output terminal of said Operational Amplifier means and in response to said Low Zero Select Command said fourth field effect transistor switch means is activated and a Low logical zero electrical manifestation appears at said output terminal of said Operational Amplifier means.

Claim 30

In an electronic test system for testing high density logic networks having n input pins and m output pins, where n and m are integer numbers respectively having any value in the range of 10 through 3,000, a pin driver circuit comprising: a first bistable device having an input terminal and an ouput terminal, said first bistable device having a first state and a second state of conductivity and being adapted to electrically manifest at said output a High command representative of said first state and a Low command representative of said second state; a second bistable device having first and second input terminals and first and second ouput terminals, said second bistable device having first and second states of conductivity; a third bistable device having first and second input terminals and first and second output terminals, said third bistable device having first and second states of conductivity; means connecting said output terminal of said first bistable device to said first input terminal of said third bistable device; data source means for impressing on said first input terminal of said second bistable device an electrical manifestation of a logical one, or an electrical manifestation of a logical zero; means connected to said input of said first bistable device for causing said device to assume said first state or said second state, said first bistable device electrically manifesting a High command when in said first state, and electrically manifesting a Low command when in said second state; a source of timing signals connected to said second input terminals of said second and third bistable devices, respectively, whereby in response to a timing signal, said second bistable device will assume its first state in response to a logical one and its second state in response to a logical zero, and said third bistable device will assume its first state in response to said High command and its second state in response to said Low command; a first AND circuit having an output, a first input connected to said first output terminal of said second bistable device, and a second input connected to said first output terminal of said third bistable device, a second AND circuit having an output, a first input connected to said output terminal of said second bistable device and a second input connected to said second output of said third bistable device, a third AND circuit having an output, a first input connected to said second output terminal of said second bistable device and a second input connected to said first output terminal of said third bistable device, and a fourth AND circuit having an output, a first input connected to said second output terminal of said second bistable device, and a second input connected to said second output terminal of said third bistable device, whereby said output of said first AND circuit electrically manifests a High-One Select Command when said second and third bistable devices are respectively in said first state, said output of said second AND circuit electrically manifests a Low-One Select Command when said second bistable device is in said first state and said third bistable device is in said second state, said output of said third AND circuit electrically manifests a High-Zero Select Command when said second bistable device is in said second state and third bistable device is in said first state, and said output of said fourth AND circuit electrically manifests a Low-Zero Select Command when said second bistable device is in said second state, and said third bistable device is in said second state; Operational Amplifier means having an input terminal and an output terminal; first field effect transistor switch means interconnecting said output terminal of said first AND circuit and said input terminal of said Operational Amplifier means, second field effect transistor switch means interconnecting said output terminal of said second AND circuit and said input terminal of said Operational Amplifier means; third field effect transistor switch means interconnecting said output terminal of said third AND circuit and said input terminal of said Operational Amplifier means, and fourth field effect transistor switch means interconnecting said output terminal of said fourth AND circuit and said input terminal of said operational amplifier means, whereby, in response to said High-One Select Command said first field effect transistor switch means is activated and a High logical one electrical manifestation appears at said output terminal of said Operational Amplifier means, in response to said Low-One Select Command, said second field effect transistor switch means is activated and a Low logical one electrical manifestation appears at said output terminal of said Operational Amplifier means, in response to said High Zero Select Command, said third field effect transistor swiTch means is activated and a High logical zero electrical manifestation appears at said output terminal of said Operational Amplifier means and in response to said Low Zero Select Command said fourth field effect transistor switch means is activated and a Low logical zero electrical manifestation appears at said output terminal of said Operational Amplifier means.

Claim 31

A pin driver circuit as claimed in claim 22 wherein said means connected to said first bistable device for causing said device to assume said first state or said second state, comprises random pulse generator means, whereby said first bistable device randomly assumes said first or second states.

Claim 32

A pin driver circuit as claimed in claim 23 wherein additional means is provided for selectively overriding said pulse generator means, and affirmatively selecting either said first state or said second state of said first bistable device.

Claim 33

In an electronic tester as claimed in claim 22 wherein additional means is provided for sensing and storing an electrical manifestation representative of the state, first or second, of said first bistable device.

Claim 34

In a tester for testing large scale integration devices having m input terminals, where m is an integer greater in magnitude than 10, said tester including: first means for providing m electrical manifestations; second means cooperating with said first means for randomly applying a first electrical manifestation, or a second electrical manifestation, on each of certain ones of said m input terminals; third means cooperating with said first means for randomly applying a third electrical manifestation, or a fourth electrical manifestation on each of the remaining ones of said m input terminals; and additional means cooperating with said first, second and third means for sensing and storing data indicative of exactly which one of said four electrical manifestations has been impressed on each of said m terminals.

Claim 35

In a tester for testing large scale integration devices having m input terminals, where m is an integer greater in magnitude than 10, said tester including: first means for providing m electrical manifestations; second means cooperating with said first means for randomly applying a first electrical manifestation, or a second electrical manifestation, on each of certain ones of said m input terminals; third means cooperating with said first means for randomly applying a third electrical manifestation, or a fourth electrical manifestation on each of the remaining ones of said m input terminals; and additional means cooperating with said first, second and third means for sensing and storing data indicative of exactly which one of said four electrical manifestations has been impressed on each of said m terminals.

Claim 36

In a tester as claimed in claim 26 wherein said first, second, third and fourth electrical manifestations are respectively unequal in voltage magnitude, said first and second electrical manifestations respectively represent logical ones, said third and fourth electrical manifestations respectively represent logical zeros, said first means and said second means each contain bistable devices, and said additional means senses the state of certain ones of said bistable devices and stores a manifestation representing the state of each of said certain ones of said bistable devices.

Claim 37

In a tester for testing large scale integration devices having m input terminals, where m is an integer greater in magnitude than 10, said tester including: first means for providing m electrical manifestations; second means cooperating with said first means for applying first electrical manifestations varying in voltage magnitude between a first value and a second value on each of certain preselected ones of said m input terminals; third means cooperating with said first means for applying second electrical manifestations varying in voltage magnitude between a third value and a fourth value on each of the remaining ones of said m input terminals, and wherein each of said first electrical manifestations vary in magnitude independently with respect to time, each of said second electrical manifestations vary independently with respect to time, and said first, second, third and fourth values of voltage magnitude are respectively unequal.

Claim 38

In a tester for testing large scale integration devices having m input terminals, where m is an integer greater in magnitude than 10, said tester including: first means for providing m electrical manifestations; second means cooperating with said first means for applying first electrical manifestations varying in voltage magnitude between a first value and a second value on each of certain preselected ones of said m input terminals; third means cooperating with said first means for applying second electrical manifestations varying in voltage magnitude between a third value and a fourth value on each of the remaining ones of said m input terminals, and wherein each of said first electrical manifestations vary in magnitude independently with respect to time, each of said second electrical manifestations vary independently with respect to time, and said first, second, third and fourth values of voltage magnitude are respectively unequal.

Claim 39

In a tester as claimed in claim 28 wherein said first electrical manifestations respectively represent logical ones, said second electrical manifestations respectively represent logical zeros and said variation in voltage magnitude of said first electrical manifestations and said second electrical manifestations are produced by a plurality of independent random pulse generator means.

Claim 40

In an electronic test system for testing high density logic networks haviNg n input pins, where n is an integer having any value in the range of 10 through 3,000, a pin driver circuit comprising: a first bistable device having an input terminal and first and second output terminals, said first bistable device having a first state and a second state of conductivity and being adapted to electrically manifest at said outputs a High command representative of said first state and a Low command representative of said second state; a second bistable device having first and second input terminals and first and second output terminals, said second bistable device having first and second states of conductivity; data source means for impressing on said first input terminal of said second bistable device an electrical manifestation of a logical one, or an electrical manifestation of a logical zero; random noise source means connected to said input of said first bistable device for causing said device to non-periodically assume said first and second states, said first bistable device electrically manifesting a High command when in said first state, and electrically manifesting a Low command when in said second state; a source of timing signals connected to said second input terminal of said second bistable device, whereby in response to a timing signal, said second bistable device will assume its first state in response to a logical one and its second state in response to a logical zero; a first AND circuit having an output, a first input connected to said first output terminal of said second bistable device, and a second input connected to said first output terminal of said first bistable device; a second AND circuit having an output, a first input connected to said first output terminal of said second bistable device and a second input connected to said first output of said first bistable device; a third AND circuit having an output, a first input connected to said second output terminal of said second bistable device and a second input connected to said second output terminal of said first bistable device; and a fourth AND circuit having an output, a first input connected to said second output terminal of said second bistable device, and a second input connected to said second output terminal of said first bistable device, whereby said output of said first AND circuit electrically manifests a High-One varying potential when said second bistable device is in said first state, said output of said second AND circuit electrically manifests a Low-One varying potential when said second bistable device is in said first state, said output of said third AND circuit electrically manifests a High-Zero varying potential when said second bistable device is in said second state, and said output of said fourth AND circuit electrically manifests a Low-Zero varying potential when said second bistable device is in said second state; Operational Amplifier means having an input terminal and an output terminal; first field effect transistor switch means interconnecting said output terminal of said first AND circuit and said input terminal of said Operational Amplifier means, second field effect transistor switch means interconnecting said output terminal of said second AND circuit and said input terminal of said Operational Amplifier means; third field effect transistor switch means interconnecting said output terminal of said third AND circuit and said input terminal of said Operational Amplifier means, and fourth field effect transistor switch means interconnecting said output terminal of said fourth AND circuit and said input terminal of said operational amplifier means, whereby, in response to said High-One varying potential and said Low-One varying potential said first and second field effect transistor switch means are respectively activated and a varying non-periodic High-Low logical one electrical manifestation appears at said output terminal of said Operational Amplifier, In response to said High Zero varying electrical potential and said Low-Zero varying potential, said third and fourth field effect transistor switch means are respectively activated and a varying non-periodic High-Low logical zero electrical manifestation appears at said output terminal of said Operational Amplifier.

Claim 41

In an electronic test system for testing high density logic networks haviNg n input pins, where n is an integer having any value in the range of 10 through 3,000, a pin driver circuit comprising: a first bistable device having an input terminal and first and second output terminals, said first bistable device having a first state and a second state of conductivity and being adapted to electrically manifest at said outputs a High command representative of said first state and a Low command representative of said second state; a second bistable device having first and second input terminals and first and second output terminals, said second bistable device having first and second states of conductivity; data source means for impressing on said first input terminal of said second bistable device an electrical manifestation of a logical one, or an electrical manifestation of a logical zero; random noise source means connected to said input of said first bistable device for causing said device to non-periodically assume said first and second states, said first bistable device electrically manifesting a High command when in said first state, and electrically manifesting a Low command when in said second state; a source of timing signals connected to said second input terminal of said second bistable device, whereby in response to a timing signal, said second bistable device will assume its first state in response to a logical one and its second state in response to a logical zero; a first AND circuit having an output, a first input connected to said first output terminal of said second bistable device, and a second input connected to said first output terminal of said first bistable device; a second AND circuit having an output, a first input connected to said first output terminal of said second bistable device and a second input connected to said first output of said first bistable device; a third AND circuit having an output, a first input connected to said second output terminal of said second bistable device and a second input connected to said second output terminal of said first bistable device; and a fourth AND circuit having an output, a first input connected to said second output terminal of said second bistable device, and a second input connected to said second output terminal of said first bistable device, whereby said output of said first AND circuit electrically manifests a High-One varying potential when said second bistable device is in said first state, said output of said second AND circuit electrically manifests a Low-One varying potential when said second bistable device is in said first state, said output of said third AND circuit electrically manifests a High-Zero varying potential when said second bistable device is in said second state, and said output of said fourth AND circuit electrically manifests a Low-Zero varying potential when said second bistable device is in said second state; Operational Amplifier means having an input terminal and an output terminal; first field effect transistor switch means interconnecting said output terminal of said first AND circuit and said input terminal of said Operational Amplifier means, second field effect transistor switch means interconnecting said output terminal of said second AND circuit and said input terminal of said Operational Amplifier means; third field effect transistor switch means interconnecting said output terminal of said third AND circuit and said input terminal of said Operational Amplifier means, and fourth field effect transistor switch means interconnecting said output terminal of said fourth AND circuit and said input terminal of said operational amplifier means, whereby, in response to said High-One varying potential and said Low-One varying potential said first and second field effect transistor switch means are respectively activated and a varying non-periodic High-Low logical one electrical manifestation appears at said output terminal of said Operational Amplifier, In response to said High Zero varying electrical potential and said Low-Zero varying potential, said third and fourth field effect transistor switch means are respectively activated and a varying non-periodic High-Low logical zero electrical manifestation appears at said output terminal of said Operational Amplifier.