EP0029322A1
Expired / Lapsed
EP
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Semiconductor memory device with redundancy
Assignee: Fujitsu Ltd
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Filing: 1980-11-05
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Granted: —
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Expires: 2000-11-05
Abstract
Abstract A semiconductor device, in which a redundancy memory cell array (2) is incorporated with a main memory cell matrix (1), is disclosed. One memory cell array is selected by two kinds of decoders and drivers (9 and 10). When the redundancy memory cell array is selected by a decoder (5), the decoder (5) disables one kind of the decoders and drivers (9) directly and, as a result, the other kind of the decoders and drivers (10) are also disabled.
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 06:28
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
221 words
A semiconductor memory device comprising: a main memory cell matrix which is divided into a plurality of sub memory cell matrixes; a redundancy memory cell array which is incorporated with said main memory cell matrix; a first decoder means for selecting one memory cell array parallel to said redundancy memory cell array within each said sub memory cell matrix, in accordance with a first part of a first address information, said first decoder means triggered by a clock signal; a second decoder means for selecting one of said sub memory cell matrixes within said main memory cell matrix, in accordance with a second part of said first address information, the driver portion of said second decoder means triggered by output signals of said first decoder means so as to select one memory cell array within said memory cell matrix; a third decoder means for selecting said redundancy memory cell array and disabling said second decoder means, in accordance with said first address information, said second decoder means being prevented from generating said output signals when said third decoder means selects said redundancy memory cell array; and a fourth decoder means for selecting one memory cell array perpendicular to said redundancy memory cell array within said main memory cell matrix and said redundancy memory array, in accordance with a second address information.
Claim 2
Dependent Claim
221 words
A semiconductor memory device comprising: a main memory cell matrix which is divided into a plurality of sub memory cell matrixes; a redundancy memory cell array which is incorporated with said main memory cell matrix; a first decoder means for selecting one memory cell array parallel to said redundancy memory cell array within each said sub memory cell matrix, in accordance with a first part of a first address information, said first decoder means triggered by a clock signal; a second decoder means for selecting one of said sub memory cell matrixes within said main memory cell matrix, in accordance with a second part of said first address information, the driver portion of said second decoder means triggered by output signals of said first decoder means so as to select one memory cell array within said memory cell matrix; a third decoder means for selecting said redundancy memory cell array and disabling said second decoder means, in accordance with said first address information, said second decoder means being prevented from generating said output signals when said third decoder means selects said redundancy memory cell array; and a fourth decoder means for selecting one memory cell array perpendicular to said redundancy memory cell array within said main memory cell matrix and said redundancy memory array, in accordance with a second address information.
Claim 3
Dependent Claim
64 words
A device as set forth in claim 1, wherein said first decoder means comprises: a plurality of first NOR gates each having an input connected to an output of said third decoder means and having inputs for receiving said first part of said first information; and a plurality of first AND gates each having an input connected to one of said first NOR gates.
Claim 4
Dependent Claim
87 words
A device as set forth in claim 1, wherein said second decoder means comprises: a plurality of second NOR gates each having inputs for receiving said second part of said first address information; and a plurality of second AND gates each having inputs connected to one of said second NOR gates and to one of the outputs of said first decoder means and each having an output connected to one memory cell array, in paralled to said redundancy memory cell array, of said main memory cell matrix.
Claim 5
Dependent Claim
43 words
A device as set forth in claim 1, wherein said third decoder means comprises a PROM for storing address. information indicating a memory cell array including a defective memory cell when said defective memory cell is detected in said main memory cell matrix.
Claim 6
Dependent Claim
16 words
A device as set forth in claim 4, wherein said PROM is of a fuse type.
Claim 7
Dependent Claim
40 words
A device as set forth in claim 1, wherein said redundancy memory cell array is incorporated with said main memory cell matrix as a row array, and said first and second address information are row and column address information, respectively.
Claim 8
Dependent Claim
40 words
A device as set forth in claim 1, wherein said redundancy memory cell array is incorporated with said main memory cell matrix as a column array, and said first and second address information are column and row address information, respectively.
References Cited (Backward Citations)
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