US4670878A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Column shift circuitry for high speed testing of semiconductor memory devices
Assignee: Texas Instruments Inc
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Filing: 1984-08-14
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Granted: 1987-06-02
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Expires: 2004-08-14
Abstract
Abstract A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.
Inventors
- 👤 Jimmie D. Childers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
154 words
A semiconductor memory device having a normal mode of operation and a test mode of operation, said device having data terminal means and control terminal means, comprising: an array of rows and columns of memory cells at a face of a semiconductor body, the rows of cells being coupled to row lines and the columns of cells being coupled to column lines, means for addressing the rows by activating the row lines, means for addressing the columns by selectively coupling one or more of the column lines to said data terminal means in said normal mode of operation, and means responsive to a test control applied to said control terminal means changing the selective coupling between said column lines and said data terminal means in said test mode of operation, whereby the column or columns coupled to said data terminal means is changed in said test mode compared to said normal mode of operation.
Claim 2
Dependent Claim
154 words
A semiconductor memory device having a normal mode of operation and a test mode of operation, said device having data terminal means and control terminal means, comprising: an array of rows and columns of memory cells at a face of a semiconductor body, the rows of cells being coupled to row lines and the columns of cells being coupled to column lines, means for addressing the rows by activating the row lines, means for addressing the columns by selectively coupling one or more of the column lines to said data terminal means in said normal mode of operation, and means responsive to a test control applied to said control terminal means changing the selective coupling between said column lines and said data terminal means in said test mode of operation, whereby the column or columns coupled to said data terminal means is changed in said test mode compared to said normal mode of operation.
Claim 3
Dependent Claim
39 words
A device according to claim 1 including separate detector means for each said column, said detector means coupled to the column lines and wherein said means for shifting includes alternate paths between the column lines and the detector means.
Claim 4
Dependent Claim
14 words
A device according to claim 2 wherein the detector means are differential sense amplifiers.
Claim 5
Dependent Claim
14 words
A device according to claim 3 wherein the cells are dynamic read/write memory cells.
Claim 6
Dependent Claim
24 words
A device according to claim 4 wherein said means for shifting includes selectively activated gating means coupled between column lines and said sense amplifiers.
Claim 7
Dependent Claim
30 words
A device according to claim 1 wherein data is written to one column in said normal mode then written from said one column to other columns in said test mode.
Claim 8
Dependent Claim
21 words
A device according to claim 6 wherein said memory cells are read/write cells, and including a sense amplifier for each column.
Claim 9
Independent Claim
102 words
A method of testing a semiconductor device contaning an array of rows and columns of memory cells, said device containing detector means for each of the columns, comprising the steps of: coupling each of said detector means to a separate one of said columns, sequentially addressing said rows while detecting operation of cells in the columns using said detector means, changing the coupling of each of said detector means for said separate one of said columns to an adjacent one of said columns, and again sequentially addressing said rows while detecting operation of the cells of the columns using said detector means.
Claim 10
Independent Claim
102 words
A method of testing a semiconductor device contaning an array of rows and columns of memory cells, said device containing detector means for each of the columns, comprising the steps of: coupling each of said detector means to a separate one of said columns, sequentially addressing said rows while detecting operation of cells in the columns using said detector means, changing the coupling of each of said detector means for said separate one of said columns to an adjacent one of said columns, and again sequentially addressing said rows while detecting operation of the cells of the columns using said detector means.
Claim 11
Dependent Claim
27 words
A method according to claim 8 including the step of coupling data to a terminal of said device from said detector means while sequentially addressing said rows.
Claim 12
Dependent Claim
26 words
A method according to claim 8 wherein each of the detector means is a differential sense amplifier coupled to the columns of cells by bit lines.
Claim 13
Dependent Claim
14 words
A method according to claim 10 wherein said cells are dynamic read/write memory cells.
Claim 14
Dependent Claim
45 words
A method according to claim 11 wherein each of said sense amplifiers is coupled to a pair of bit lines for either the column of cells aligned with it, or the column of cells to the left, or the column of cells to the right.
Claim 15
Dependent Claim
36 words
A method according to claim 12 including the step of coupling data to or from a terminal of said device from selected ones of said sense amplifiers using column addressing means, while sequentially addressing said rows.
Claim 16
Independent Claim
94 words
A method of writing data into a semiconductor device containing an array of rows and columns of memory cells, comprising the steps of: writing a data pattern to one of said columns by sequentially addressing said rows while coupling data bits to the columns from a terminal of the device, then writing said data pattern to all other columns of said device by sequentially addressing said rows while coupling said one column to a first adjacent column, then coupling said first adjacent columns to a second adjacent column, until all columns are written into.
Claim 17
Independent Claim
94 words
A method of writing data into a semiconductor device containing an array of rows and columns of memory cells, comprising the steps of: writing a data pattern to one of said columns by sequentially addressing said rows while coupling data bits to the columns from a terminal of the device, then writing said data pattern to all other columns of said device by sequentially addressing said rows while coupling said one column to a first adjacent column, then coupling said first adjacent columns to a second adjacent column, until all columns are written into.
Claim 18
Dependent Claim
30 words
A method according to claim 14 wherein said cells are read/write memory cells, and a plurality of sense amplifiers are coupled separately to each of said columns by bit lines.
Claim 19
Dependent Claim
37 words
A method according to claim 15 including the step of selectively coupling said sense amplifiers to a given column of cells or an adjacent column of cells in response to a test control input to the device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |