Semiconductor memory device

Claim 2

A semiconductor memory device having a write mode and a read mode, comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during the read mode and connecting said selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during the write mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct.

Claim 3

A semiconductor memory device having normal and read test modes, comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks and comprising a positive data bus and a negative data bus; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during the read mode and connecting said selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during the normal mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct, said read test circuit comprising: an output terminal; a plurality of first transistors each having a drain operatively connected to said first power supply terminal, a gate operatively connected to one of the positive data buses and a source operatively connected to said output terminal; a plurality of second transistors each having a drain operatively connected to said output terminal, a gate operatively connected to one of the negative data buses, and a source; and a third transistor having a drain operatively connected to the sources of said second transistors, a gate, and a source operatively connected to said power supply terminal, the potential of the gate of said third transistor being set at a first level so as to be in a non-conductive state when said third transistor is in the normal mode and being set at a second level so as to be in a conductive state when said third transistor is in the read test mode.

Claim 4

A semiconductor memory device having normal and read test modes, comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks and comprising a positive data bus and a negative data bus; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during the read mode and connecting said selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during the normal mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct, said read test circuit comprising: an output terminal; a plurality of first transistors each having a drain operatively connected to said first power supply terminal, a gate operatively connected to one of the positive data buses and a source operatively connected to said output terminal; a plurality of second transistors each having a drain operatively connected to said output terminal, a gate operatively connected to one of the negative data buses, and a source; and a third transistor having a drain operatively connected to the sources of said second transistors, a gate, and a source operatively connected to said power supply terminal, the potential of the gate of said third transistor being set at a first level so as to be in a non-conductive state when said third transistor is in the normal mode and being set at a second level so as to be in a conductive state when said third transistor is in the read test mode.

Claim 5

A semiconductor memory device as set forth in claim 2, wherein said read test circuit further comprises a plurality of resistors each operatively connected in series to one of said first and second transistors.

Claim 6

A semiconductor memory device as set forth in claim 2, wherein said read test circuit further comprises an inverter circuit operatively connected between the gate of said third transistor and said first power supply.

Claim 7

A semiconductor memory device comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks and comprising a positive data bus and a negative data bus; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during a read mode and connecting said selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during a write mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct, said read test circuit comprising: first and second resistors operatively connected to said second power supply terminal; first and second output terminals each operatively connected to said first and second resistors, respectively; a plurality of first transistors operatively connected in series between said first output terminal and said first power supply terminal, each of said first transistors having a gate operatively connected to one of the positive data buses; and a plurality of second transistors operatively connected in series between said second output terminal and said first power supply terminal, each of said second transistors having a gate connected to one of the negative data buses.

Claim 8

A semiconductor memory device comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks and comprising a positive data bus and a negative data bus; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during a read mode and connecting said selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during a write mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct, said read test circuit comprising: first and second resistors operatively connected to said second power supply terminal; first and second output terminals each operatively connected to said first and second resistors, respectively; a plurality of first transistors operatively connected in series between said first output terminal and said first power supply terminal, each of said first transistors having a gate operatively connected to one of the positive data buses; and a plurality of second transistors operatively connected in series between said second output terminal and said first power supply terminal, each of said second transistors having a gate connected to one of the negative data buses.

Claim 9

A semiconductor memory device, comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during a read mode and connecting the selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during a write mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising: simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; a plurality of pairs of transfer gate transistors, each pair operatively connected to one of said pairs of data buses, for receiving input data; and a plurality of decoders, each operatively connected to one of said pairs of transfer gate transistors, for selecting one pair of said pairs of data buses; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct.

Claim 10

A semiconductor memory device, comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses, each pair being operatively connected to one of said memory blocks; cell selection means, operatively connected to said memory blocks, for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses; write data buses; read data buses; a block selection circuit, operatively connected to said pairs of data buses, said read data buses and said write data buses, for selecting one pair of said pairs of data buses during a read mode and connecting the selected pair of data buses to said read data buses, and for selecting one pair of said pairs of data buses during a write mode and connecting the selected pair of data buses to said write data buses, said block selection circuit comprising: simultaneous write means for selecting all of said pairs of data buses to simultaneously write input data in all of the selected memory cells selected by said cell selection means; a plurality of pairs of transfer gate transistors, each pair operatively connected to one of said pairs of data buses, for receiving input data; and a plurality of decoders, each operatively connected to one of said pairs of transfer gate transistors, for selecting one pair of said pairs of data buses; and a read test circuit, operatively connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses and for checking simultaneously whether or not the data on said data buses transmitted from the selected memory cells is correct.

Claim 11

A semiconductor memory device as set forth in claim 5, wherein said block selection circuit further comprises simultaneous write means, operatively connected to each of said decoders, for enabling said decoders to select all of said pairs of data buses so as to simultaneously write input data into all of the selected memory cells selected by said cell selection means.

Claim 12

A semiconductor memory device as set forth in claim 7, wherein said simultaneous write means comprises: a write transistor operatively connected between said decoders and said second power supply; and a resistor operatively connected between said write transistor and said first power supply.