US4342103A
Expired / Lapsed
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Address buffer circuit
Assignee: Fujitsu Ltd
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Filing: 1980-07-23
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Granted: 1982-07-27
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Expires: 2000-07-23
Abstract
Abstract An address buffer circuit is used in a memory device, for example in an EPROM device, and enables high speed testing of the memory device. The address buffer circuit can output "1" or "0" from both a positive output terminal and a negative output terminal when an input word address signal having a signal level different from the usual signal level is applied to an input of the address buffer circuit, so that a plurality of word lines can be selected at a time.
Inventors
- 👤 Mitsuo Higuchi
- 👤 Kiyoshi Miyasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:06
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/46; G11C29/50; G11C8/00; G11C8/06; G11C8/12; G11C16/00; G11C16/02; G11C16/04
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
205 words
An address buffer circuit for receiving an input address signal, having first and second levels, and for supplying, as outputs, a positive output signal (A) and a negative output signal (A) to an address decoder, said address buffer circuit comprising: a first input circuit for receiving the input address signal, said first input circuit operated by the first level of the input address signal; a second input circuit for receiving the input address signal and for providing, as an output, a switching signal when the second level of the input address signal is applied thereto; inverter means, operatively connected to said first input circuit, for providing positive and negative input address signals; a positive output buffer, operatively connected to said inverter means, for providing said positive output signal (A) to said address decoder; a negative output buffer, operatively connected to said inverter means, for providing said negative output signal (A) to said address decoder; and clamping means, operatively connected to said positive and negative output buffers and to said second input circuit, for clamping both said positive output signal (A) and said negative output signal (A) to a "high" or "low" logic level when said switching signal from said second input circuit is supplied thereto.
Claim 2
Dependent Claim
205 words
An address buffer circuit for receiving an input address signal, having first and second levels, and for supplying, as outputs, a positive output signal (A) and a negative output signal (A) to an address decoder, said address buffer circuit comprising: a first input circuit for receiving the input address signal, said first input circuit operated by the first level of the input address signal; a second input circuit for receiving the input address signal and for providing, as an output, a switching signal when the second level of the input address signal is applied thereto; inverter means, operatively connected to said first input circuit, for providing positive and negative input address signals; a positive output buffer, operatively connected to said inverter means, for providing said positive output signal (A) to said address decoder; a negative output buffer, operatively connected to said inverter means, for providing said negative output signal (A) to said address decoder; and clamping means, operatively connected to said positive and negative output buffers and to said second input circuit, for clamping both said positive output signal (A) and said negative output signal (A) to a "high" or "low" logic level when said switching signal from said second input circuit is supplied thereto.
Claim 3
Dependent Claim
47 words
An address buffer circuit as set forth in claim 1, wherein said input address signal also has a base level of a first logic level and wherein the first level of said input address signal is of a second logic level higher than said first logic level.
Claim 4
Dependent Claim
53 words
An address buffer circuit as set forth in claim 2, wherein the second level of the input address signal is of a third logic level higher than said second logic level and wherein said second input circuit outputs the switching signal when the input address signal of the second level is applied thereto.
Claim 5
Dependent Claim
66 words
An address buffer circuit as set forth in claim 1, wherein said first input circuit comprises a field effect transistor circuit and wherein said second input circuit comprises a field effect transistor having an insulation layer between the gate electrode and the substrate which is of a thickness greater than that of the corresponding insulation layer of the field effect transistors comprising said first input circuit.
Claim 6
Dependent Claim
58 words
An address buffer circuit as set forth in claim 1, wherein said first input circuit comprises a field effect transistor circuit, and wherein said second input circuit comprises a field effect transistor having a semiconductor substrate which has a higher impurity concentration than that of the semiconductor substrates of the field effect transistors comprising said first input circuit.
Claim 7
Dependent Claim
48 words
An address buffer circuit as set forth in claim 1, wherein said second input circuit comprises at least one gate-drain coupled field effect transistor and a field effect transistor having a source electrode which is connected to ground through said at least one gate-drain coupled field effect transistor.
Claim 8
Dependent Claim
88 words
An address buffer circuit as set forth in claim 1, 2, 3, 4, 5 or 6, wherein each of said positive and negative output buffers has an output terminal, wherein said clamping means comprises first and second switching transistors which are respectively connected between the output terminal of said positive output buffer and the ground, and between the output terminal of said negative output buffer and the ground, and wherein said first and second switching transistors are turned on by said switching signal from said second input circuit.
Claim 9
Dependent Claim
94 words
An address buffer circuit as set forth in claim 7, further comprising a voltage source, wherein each of said positive and negative output buffers has a voltage supply terminal, and wherein said clamping means further comprises first and second shut off transistors which are respectively connected between the voltage supply terminal of said positive output buffer and the voltage source and between the voltage supply terminal of said negative output buffer and the voltage source, said first and second shut off transistors being cut off by said switching signal from said second input circuit.
Claim 10
Dependent Claim
87 words
An address buffer circuit as set forth in claim 1, 2, 3, 4, 5 or 6, wherein each of said positive and negative output buffers has a grounding terminal, and wherein said clamping means comprises first and second shut off transistors which are respectively connected between the grounding terminal of said positive output buffer and ground, and between the grounding terminal of said negative output buffer and ground, said first and second shut off transistors being cut off by said switching signal from said second input circuit.
Claim 11
Dependent Claim
187 words
An address buffer circuit receiving an input address signal having first, second and third logic levels, and providing an output address signal and an inverted output address signal to an address decoder, said address buffer circuit comprising: input means for receiving the input address signal and for generating first and second output signals; an input buffer circuit for receiving the input address signal and for providing, as an output, a switching signal when the third level of the input address signal is received; a positive output buffer circuit, operatively connected to said input means, for receiving said first output signal and for providing said output address signal to the address decoder; a negative output buffer circuit, operatively connected to said input means, for receiving said second output signal and for providing said inverted output address signal to the address decoder; clamping means, operatively connected to said positive and negative output buffer circuits and to said input buffer circuit, for clamping both said output address signal and said inverted output address signal to a predetermined logic level when said switching signal is received from said input buffer circuit.
Claim 12
Dependent Claim
187 words
An address buffer circuit receiving an input address signal having first, second and third logic levels, and providing an output address signal and an inverted output address signal to an address decoder, said address buffer circuit comprising: input means for receiving the input address signal and for generating first and second output signals; an input buffer circuit for receiving the input address signal and for providing, as an output, a switching signal when the third level of the input address signal is received; a positive output buffer circuit, operatively connected to said input means, for receiving said first output signal and for providing said output address signal to the address decoder; a negative output buffer circuit, operatively connected to said input means, for receiving said second output signal and for providing said inverted output address signal to the address decoder; clamping means, operatively connected to said positive and negative output buffer circuits and to said input buffer circuit, for clamping both said output address signal and said inverted output address signal to a predetermined logic level when said switching signal is received from said input buffer circuit.
Claim 13
Dependent Claim
49 words
An address buffer circuit as set forth in claim 10, wherein the input address signal is at the third level when a testing operation is to be performed and wherein said input buffer circuit provides said switching signal in response to the third level of the input address signal.
Claim 14
Dependent Claim
62 words
An address buffer circuit as set forth in claim 10, wherein said input means comprises a first field effect transistor and wherein said input buffer circuit comprises a second field effect transistor having an insulation layer between the gate electrode and the substrate which is of a thickness greater than that of the corresponding insulation layer of said first field effect transistor.
Claim 15
Dependent Claim
54 words
An address buffer circuit as set forth in claim 10, wherein said input means comprises a first field effect transistor and wherein said input buffer circuit comprises a second field effect transistor having a semiconductor substrate which has a higher impurity concentration than that of the semiconductor substrate of said first field effect transistor.
Claim 16
Dependent Claim
49 words
An address buffer circuit as set forth in claim 10, wherein said input buffer circuit comprises at least two gate-drain coupled field effect transistors and a first field effect transistor having a source electrode which is connected to ground through said at least two gate-drain coupled field effect transistors.
Claim 17
Dependent Claim
87 words
An address buffer circuit as set forth in claim 10 or 14, wherein each of said positive and negative output buffer circuits has an output terminal, wherein said clamping means comprises first and second switching transistors which are respectively connected between the output terminal of said positive output buffer circuit and the ground, and between the output terminal of said negative output buffer circuit and the ground, and wherein said first and second switching transistors are turned on by said switching signal from said input buffer circuit.
Claim 18
Dependent Claim
97 words
An address buffer circuit as set forth in claim 15, further comprising a voltage source, wherein each of said positive and negative output buffer circuits has a voltage supply terminal, and wherein said clamping means further comprises first and second shut off transistors which are respectively connected between the voltage supply terminal of said positive output buffer circuit and the voltage source and between the voltage supply terminal of said negative output buffer circuit and the voltage source, said first and second shut off transistors being shut off by said switching signal from said input buffer circuit.
Claim 19
Dependent Claim
84 words
An address buffer circuit as set forth in claim 10 or 11, wherein each of said positive and negative output buffer circuits has a grounding terminal, and wherein said clamping means comprises first and second shut off transistors respectively connected between the grounding terminal of said positive output buffer circuit and ground, and between the grounding terminal of said negative output buffer circuit and ground, said first and second shut off transistors being shut off by said switching signal from said input buffer circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-26 | 1986-01-25 | 1986-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-26 | 1990-01-25 | 1990-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-26 | 1994-01-25 | 1994-07-27 | $7700.00 | Window Closed / Lapsed |