Address buffer circuit for high speed semiconductor memory

Claim 2

An input buffer circuit for an address input of a semiconductor memory device, comprising: a pair of driver transistors substantially unbalanced in size and characteristic, each driver transistor having a control electrode and two output electrodes, the driver transistors being cross coupled by connection of the control electrode of each to an output electrode of the other; a pair of precharge transistors, one for each of the driver transistors, the precharge transistors being substantially balanced in size and characteristic, each of the precharge transistors being connected in series with one of the driver transistors and a supply voltage; means connected to turn on the pair of precharge transistors and to turn off the precharge transistors at a preselected time in an operating cycle; means to short output electrodes of the pair of cross coupled driver transistors together to equalize the voltages on such output electrodes prior to said preselected time in an operating cycle; means connected to one of the output electrodes of one of said pair of cross coupled driver transistors to couple said one of the output electrodes to a reference potential when said address input is present beginning at said preselected time; means for applying a charge to each of the output electrodes a short delay time after said preselected time to retard discharge of one of the output electrodes; and a pair of address signal output circuits, each of which has an input connected to an output electrode of a different one of the pair of cross coupled driver transistors and responsive to the voltage level thereof beginning at a time after said short delay time during an operating cycle, one of the pair of address signal output circuits producing an address signal and the other producing the complement of the address signal.

Claim 3

An input buffer circuit according to claim 1 wherein the output electrodes of each of said pair of cross coupled driver transistors are source and drain electrodes and the control electrode is a gate, and the drain electrode of each is directly coupled to the gate of the other.

Claim 4

An input buffer circuit according to claim 2 wherein each of the pair of precharge transistors has a source, a drain and a gate, and the source of each is directly connected to the drain electrode of a different one of the pair of cross coupled driver transistors.

Claim 5

An input buffer circuit according to claim 3 wherein the means to short output electrodes is an equalizer transistor having a source-drain path connecting the drains of the driver transistors.

Claim 6

An input buffer circuit according to claim 4 wherein a clock source having a voltage level higher than said supply voltage is connected to the gates of the precharge transistors and the equalizer transistor, such voltage level going to zero at said preselected time in each operating cycle.

Claim 7

An input buffer circuit according to claim 1 wherein the means for applying a charge to the output electrodes of the cross coupled driver transistors comprises a pair of MOS capacitors each separately connected between the drain electrode of one of the pair of cross coupled driver transistors and a source of recurring pulses which being at said short delay after said preselected time and terminate prior to said preselected time during each operating cycle.

Claim 8

An input buffer circuit according to claim 6 wherein the means to couple said one output electrode of one of the pair of cross coupled driver transistors to a reference potential comprises two input transistors having their source-drain paths connected in a series path between the drain of one of the pair of cross coupled driver transistors and reference potential.

Claim 9

An input buffer circuit according to claim 7 wherein one of the two input transistors has its gate connected to an address input terminal and the other of the two has its gate connected to a source of recurring pulses which begin at about said preselected time during each operating cycle.

Claim 10

An input buffer circuit according to claim 8 wherein said one of the two input transistors exhibits a capacitance of a given magnitude, and the address input terminal is coupled to the drain of the other of said pair of cross coupled driver transistors by capacitive means of substantially the same magnitude as that of said one of the two input transistors.

Claim 11

An input buffer circuit according to claim 8 wherein the pair of address signal output circuits each comprises first, second and third MOS transistors each of which has a source, a drain and a gate, the source-drain paths of the first and second transistors being connected in series between supply means and a reference potential and the sourcedrain path of the third transistor being connected in parallel with the source-drain path of the second transistor.

Claim 12

An input buffer circuit according to claim 10 wherein the input of each of the address signal output circuits comprises a connection from the drain of a different one of the pair of cross coupled driver transistors to the gate of the first transistor in one of the output circuits and to the gate of the second transistor in the other of the output circuits.

Claim 13

An input buffer circuit according to claim 11 wherein the gates of the third transistors in each of the output circuits are both connected to a source of recurring pulses which terminate at about said preselected time during each operating cycle.

Claim 14

An input buffer circuit according to claim 12 wherein said supply means is a source of recurring pulses which begin after said short delay time in each operation cycle.

Claim 15

An input buffer circuit according to claim 13 wherein the address signal and the complement of the address signal are produced at the node between the first and second MOS transistors in the pair of address signal output circuits.

Claim 16

An input buffer circuit according to claim 14 wherein means, having an input connected to receive the address signal and the complement of the address signal and having an output coupled to a gate of a series transistor which has its source-drain path in series between the address input terminal and said one of the input transistors is operative to terminate response to an address input after an address signal or complement occurs.

Claim 17

An input buffer circuit according to claim 8 wherein feedback means responsive to the occurence of the address signal and the complement of the address signal from the address signal output circuits produces an input to means connected to gate an address input from said address input terminal to said one of the input transistors.

Claim 18

An input latch for a semiconductor integrated circuit of the type employing insulated gate field effect transistors, comprising: a pair of driver transistors unbalanced in characteristic, each driver transistor having a source-drain path and a gate, a pair of precharge transistors each having a source-drain path and a gate, means connecting the source-drain path of each of the driver transistors in series with the source-drain path of a different one of the precharge transistors and connecting each series-connected driver and precharge transistor across supply voltage means, a pair of sense nodes, one between each of the series-connected source-drain paths of the driver and precharge transistors, cross coupling means connecting each sense node to the gate of the other driver transistors, means connected to the gates of the precharge transistors to turn on the precharge transistors prior to a first selected time in an operating cycle, and to turn off the precharge transistors at a said first selected time, means connected to the pair of sense nodes to equalize the voltages thereon prior to said first selected time in an operating cycle, input means connected to one of the sense nodes to couple such node to a reference potential when an input signal is present at a time beginning at said first selected time in an operating cycle, charge means connected separately to each of the sense nodes to apply a charge thereto at second time which is after said first selected time in each operating cycle, signal output circuit means having input means coupled to at least one of the sense nodes and responsive to the voltage thereon beginning at a third selected time which is after the second selected time in an operating cycle, the signal output circuit means producing a signal during a period of time beginning after said third selected time in an operating cycle.

Claim 19

An input latch for a semiconductor integrated circuit of the type employing insulated gate field effect transistors, comprising: a pair of driver transistors unbalanced in characteristic, each driver transistor having a source-drain path and a gate, a pair of precharge transistors each having a source-drain path and a gate, means connecting the source-drain path of each of the driver transistors in series with the source-drain path of a different one of the precharge transistors and connecting each series-connected driver and precharge transistor across supply voltage means, a pair of sense nodes, one between each of the series-connected source-drain paths of the driver and precharge transistors, cross coupling means connecting each sense node to the gate of the other driver transistors, means connected to the gates of the precharge transistors to turn on the precharge transistors prior to a first selected time in an operating cycle, and to turn off the precharge transistors at a said first selected time, means connected to the pair of sense nodes to equalize the voltages thereon prior to said first selected time in an operating cycle, input means connected to one of the sense nodes to couple such node to a reference potential when an input signal is present at a time beginning at said first selected time in an operating cycle, charge means connected separately to each of the sense nodes to apply a charge thereto at second time which is after said first selected time in each operating cycle, signal output circuit means having input means coupled to at least one of the sense nodes and responsive to the voltage thereon beginning at a third selected time which is after the second selected time in an operating cycle, the signal output circuit means producing a signal during a period of time beginning after said third selected time in an operating cycle.

Claim 20

An input latch according to claim 17 wherein the sourcedrain paths of the driver transistors remote from the sense nodes are connected to reference potential through two grounding transistors, one of which cuts on at said first selected time and the other of which cuts on at said second selected time.

Claim 21

An input latch according to claim 18 wherein the one grounding transistor is much smaller than the other grounding transistor.