US3848237A
Expired / Lapsed
US
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High speed mos random access read/write memory device
Assignee: Advanced Memory Systems Inc
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Filing: 1973-02-20
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Granted: 1974-11-12
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Expires: 1993-02-20
Abstract
Abstract A Random Access Read/Write Memory utilizing field effect devices having a matrix of three field effect device memory cells, data control cells and buffer circuitry for signal conditioning and TTL buffering. The memory utilizes a unique voltage source circuit which provides TTL compatability even when using high threshold field effect device processing in the formation of the integrated circuit read/write memory. Other unique features include a unique exclusive OR circuit for the data write driver and the sense circuit and a special circuit to decrease the response time of the read output line.
Inventors
- 👤 M Geilhufe
- 👤 R Mehta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G11C11/403; G11C11/405; G11C11/406; G11C11/4082; G11C11/4085; G11C11/4087; G11C11/409; G11C11/4091; G11C11/4096
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
468 words
In an MOS semiconductor memory, a plurality of memory cell means arranged in rows and columns, each said memory cell means having a dynamic storage node and being a means coupled to a data sense line for that row and responsive to a decoded first clock signal for that column to set said data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of data control cell means, each said data control cell means being in one of said columns, each said data control cell means having a dynamic storage node and being a means coupled to a data control line and being responsive to a decoded first clock signal for that column to set a data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of TTL buffer means, each said TTL buffer means being a means for receiving a plurality of TTL address logic signals and presenting, as outputs thereof, the equivalent MOS compatible logic signals and the inverse thereof; a plurality of X decoder means, each said X decoder means being associated with a row of said memory cell means and being a means for receiving a unique combination of outputs from a first group of said TTL buffer means and for coupling said data sense line for that row to a read output line following the occurrence of a specific and unique combination of inputs to said first group of TTL buffer means; a plurality of Y decoder means, each said Y decoder means being associated with a column of said memory cell means and said data control cell in said column, and being a means for receiving a unique combination of outputs from a second group of said TTL buffer means and for coupling said first clock signal and said second clock signal, as said decoded first clock signal and said decoded second clock signal, to all said cells in the respective column following the occurrence of a specific and unique combination of inputs to said second combination of TTL buffer means; and sensing means for sensing the states of said read output line and said data control line and for providing a logic data output signal which is a first logic state signal when said read output line and said data control line is in the same state, and is a second logic state when said read output line and said data control line are in opposite states.
Claim 2
Dependent Claim
468 words
In an MOS semiconductor memory, a plurality of memory cell means arranged in rows and columns, each said memory cell means having a dynamic storage node and being a means coupled to a data sense line for that row and responsive to a decoded first clock signal for that column to set said data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of data control cell means, each said data control cell means being in one of said columns, each said data control cell means having a dynamic storage node and being a means coupled to a data control line and being responsive to a decoded first clock signal for that column to set a data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of TTL buffer means, each said TTL buffer means being a means for receiving a plurality of TTL address logic signals and presenting, as outputs thereof, the equivalent MOS compatible logic signals and the inverse thereof; a plurality of X decoder means, each said X decoder means being associated with a row of said memory cell means and being a means for receiving a unique combination of outputs from a first group of said TTL buffer means and for coupling said data sense line for that row to a read output line following the occurrence of a specific and unique combination of inputs to said first group of TTL buffer means; a plurality of Y decoder means, each said Y decoder means being associated with a column of said memory cell means and said data control cell in said column, and being a means for receiving a unique combination of outputs from a second group of said TTL buffer means and for coupling said first clock signal and said second clock signal, as said decoded first clock signal and said decoded second clock signal, to all said cells in the respective column following the occurrence of a specific and unique combination of inputs to said second combination of TTL buffer means; and sensing means for sensing the states of said read output line and said data control line and for providing a logic data output signal which is a first logic state signal when said read output line and said data control line is in the same state, and is a second logic state when said read output line and said data control line are in opposite states.
Claim 3
Dependent Claim
193 words
The memory of claim 1 further comprised of a read/write generator means and a write driver means, said read/write generator being coupled to said plurality of X decoder means and being a means for receiving a TTL read/write logic signal and for providing a write command signal to said X decoder means upon the occurrence of said TTL write logic signal, said write driver means being a means for receiving a TTL data input logic signal and a signal from said data control line and for providing a write driver signal to said plurality of X decoder means, upon the occurrence of a timing signal, having one logic state when said TTL data input logic signal and said data control line are at the same state, and another logic state when said TTL data input logic signal and said data control line are in opposite states, each said X decoder means further being a means for coupling said write driver signal to said data sense line upon the occurrence of said write command signal following said occurrence of a specific and unique combination of inputs to said frist combination of TTL buffer means.
Claim 4
Dependent Claim
147 words
The memory of claim 1 further comprised of a voltage source means, said voltage source means being a means for providing an output voltage different from a predetermined voltage between the first and second voltages characteristic of TTL logic states by an amount substantially equal to the threshold voltage of the MOS devices of said semiconductor memory, at least one of said means receiving a TTL input signal having, as an input device, a first MOS device having a first and second region and an insulated gate, said first region being coupled to said output voltage of said voltage source means and said gate of said first MOS device being coupled to said TTL input signal, whereby the said voltage of said voltage source may compensate for threshold voltage variations in said MOS device to maintain the TTL compatibility of the circuit receiving said TTL input signal.
Claim 5
Dependent Claim
75 words
The memory of claim 3 wherein said voltage source is comprised of a second MOS device having first and second regions and an insulated gate, said second MOS device having its said first region coupled to a first power supply terminal, its said second region providing said output voltage of said voltage source and being coupled to said second power supply terminal through said load device, and its said gate coupled to a predetermined voltage.
Claim 6
Dependent Claim
122 words
The memory of claim 4 further comprised of a third MOS device and said load device is a fourth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said third MOS device by being coupled to said second region of said third MOS device, said gate and said first region of said third MOS device being coupled to said first power supply terminal, said fourth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 7
Dependent Claim
98 words
The memory of claim 4 further comprised of third and fourth MOS devices each having first and second regions and a gate, said first region of said third MOS device and said gates of said third and fourth MOS devices being coupled to a first power supply terminal, said second region of said third MOS device being coupled to said first region of said fourth MOS device and to said gate of said second MOS device to provide said predetermined voltage thereto, said second region of said fourth MOS device being coupled to said second power supply terminal.
Claim 8
Dependent Claim
122 words
The memory of claim 4 further comprised of a fifth MOS device and said load device is a sixth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said fifth MOS device by being coupled to said second region of said fifth MOS device, said gate and said first region of said fifth MOS device being coupled to said first power supply terminal, said sixth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 9
Dependent Claim
75 words
The memory of claim 1 wherein said sensing means is comprised of first and second MOS devices, each having first and second regions and an insulated gate, said first and secoNd MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device, and said second MOS device having its said second region coupled to said gate of said first MOS device.
Claim 10
Dependent Claim
74 words
The memory of claim 8 further comprised of a coupling means, and means for simultaneously applying a first signal to said gate of said first MOS device responsive to the state of the one of said data control cells in an addressed column, and a second signal to said gate of said second MOS device responsive to the state of the one of said memory cells in an addressed column and an addressed row.
Claim 11
Dependent Claim
70 words
The memory of claim 1 further comprised of trigger means coupled to said read output line, said trigger means being a means for the sensing of the change of state of said read output line from a first state toward a second state and to provide a drive voltage to said read output line upon said sensing of the change to drive said read output line toward said second state.
Claim 12
Dependent Claim
76 words
The memory of claim 2 wherein said write driver means is comprised of first and second MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device, and said second MOS device having its said second region coupled to said gate of said first MOS device.
Claim 13
Dependent Claim
66 words
The memory of claim 11 further comprised of a coupling means, and means for simultaneously applying a first signal to said gate of said first MOS device responsive to the state of the one of said data control cells in an addressed column, and a second signal to said gate of said second MOS device responsive to the state of said TTL data input logic signal.
Claim 14
Dependent Claim
160 words
The memory of claim 1 further comprised of a delay means and coupling means, and wherein said X decoder means is a means for receiving a unique combination of outputs from a first group of said TTL buffer means and for coupling said data sense line for that row to a read output line following the occurrence of a specific and unique combination of inputs to said first group of TTL buffer means, and upon the occurrence of a delayed clock signal, the output of said delay means being coupled to said X decoder means through said coupling means, said delay means being an additional cell means having a dynamic storage node and being responsive to said first clock signal to set said output of said delay means to a logic state opposite the logic state of its said storage node, and responsive to said second clock signal for setting the state of its said output into said storage node.
Claim 15
Dependent Claim
182 words
In an MOS memory circuit wherein first and second logic signals must be compared and a third logic signal provided which has a first logic state when said first and second logic signals are in the same logic states, a means for providing said third logic signal comprising; an input means, a coupling means and first and second MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device and said second MOS device having its said second region coupled to said gate of said first MOS device, said input means being coupled to the gates of said first and second MOS devices and being a means for substantially simultaneously coupling said first and second logic signals to said gates of said first and second MOS devices respectively, said coupling means being a means coupled to said first regions of said first and second MOS devices for providing said third logic signal.
Claim 16
Dependent Claim
182 words
In an MOS memory circuit wherein first and second logic signals must be compared and a third logic signal provided which has a first logic state when said first and second logic signals are in the same logic states, a means for providing said third logic signal comprising; an input means, a coupling means and first and second MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device and said second MOS device having its said second region coupled to said gate of said first MOS device, said input means being coupled to the gates of said first and second MOS devices and being a means for substantially simultaneously coupling said first and second logic signals to said gates of said first and second MOS devices respectively, said coupling means being a means coupled to said first regions of said first and second MOS devices for providing said third logic signal.
Claim 17
Dependent Claim
152 words
A means for providing compatibility of an MOS logic circuit with a logic signal input to an integrated circuit independent of the reasonable variation of the threshold volTage of the MOS devices comprising a first MOS device having first and second regions and an insulated gate, a voltage source circuit means and an MOS logic circuit means, said first MOS device having its first region coupled to said MOS logic circuit means, its second region coupled to said voltage source means, and its gate coupled to said logic signal input, said MOS logic circuit means being a means for providing a logic signal output responsive to the conduction state of said first MOS device, said voltage source means being a means for providing a voltage different from a predetermined voltage between the voltages of said logic signal input, by an amount approximately equal to the threshold voltage of said first MOS device.
Claim 18
Dependent Claim
152 words
A means for providing compatibility of an MOS logic circuit with a logic signal input to an integrated circuit independent of the reasonable variation of the threshold volTage of the MOS devices comprising a first MOS device having first and second regions and an insulated gate, a voltage source circuit means and an MOS logic circuit means, said first MOS device having its first region coupled to said MOS logic circuit means, its second region coupled to said voltage source means, and its gate coupled to said logic signal input, said MOS logic circuit means being a means for providing a logic signal output responsive to the conduction state of said first MOS device, said voltage source means being a means for providing a voltage different from a predetermined voltage between the voltages of said logic signal input, by an amount approximately equal to the threshold voltage of said first MOS device.
Claim 19
Dependent Claim
75 words
The memory of claim 15 wherein said voltage source is comprised of a second MOS device having first and second regions and an insulated gate, said second MOS device having its said first region coupled to a first power supply terminal, its said second region providing said output voltage of said voltage source and being coupled to a second power supply terminal through said load device, and its said gate coupled to a predetermined voltage.
Claim 20
Dependent Claim
122 words
The memory of claim 15 further comprised of a third MOS device and said load device is a fourth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said third MOS device by being coupled to said second region of said third MOS device, said gate and said first region of said third MOS device being coupled to said first power supply terminal, said fourth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 21
Dependent Claim
98 words
The memory of claim 15 further comprised of third and fourth MOS devices each having first and second regions and a gate, said first region of said third MOS device and said gates of said third and fourth MOS devices being coupled to a first power supply terminal, said second region of said third MOS device being coupled to said first region of said fourth MOS device and to said gate of said second MOS device to provide said predetermined voltage thereto, said second region of said fourth MOS device being coupled to said second power supply terminal.
Claim 22
Dependent Claim
122 words
The memory of claim 15 further comprised of a fifth MOS device and said load device is a sixth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said fifth MOS device by being coupled to said second region of said fifth MOS device, said gate and said first region of said fifth MOS device being coupled to said first power supply terminal, said sixth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 23
Dependent Claim
461 words
In an MOS semiconductor memory, a plurality of memory cell means arranged in rows and columns, each said memory cell means having a dynamic storage node and being a means coupled to a data sense line for that row and responsive to a decoded first clock signal for that column to set said data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of data control cell means, each said data control cell means being in one of said columns, each said data control cell means having a dynamic storage node and being a means coupled to a data control line and being responsive to a decoded first clock signal for that column to set a data sense linE to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of buffer means, each said buffer means being a means for receiving a plurality of address logic signals and presenting, as outputs thereof, the equivalent MOS compatible logic signals and the inverse thereof; a plurality of X decoder means, each said X decoder means being associated with a row of said memory cell means and being a means for receiving a unique combination of outputs from a first group of said buffer means and for coupling said data sense line for that row to a read output line following the occurrence of a specific and unique combination of inputs to said first group of buffer means; a plurality of Y decoder means, each said Y decoder means being associated with a column of said memory cell means and said data control cell in said column, and being a means for receiving a unique combination of outputs from a second group of said buffer means and for coupling said first clock signal and said second clock signal, as said decoded first clock signal and said decoded second clock signal, to all said cells in the respective column following the occurrence of a specific and unique combination of inputs to said second combination of buffer means; and sensing means for sensing the states of said read output line and said data control line and for providing a logic data output signal which is a first logic state signal when said read output line and said data control line is in the same state, and is a second logic state when said read output line and said data control line are in opposite states.
Claim 24
Dependent Claim
461 words
In an MOS semiconductor memory, a plurality of memory cell means arranged in rows and columns, each said memory cell means having a dynamic storage node and being a means coupled to a data sense line for that row and responsive to a decoded first clock signal for that column to set said data sense line to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of data control cell means, each said data control cell means being in one of said columns, each said data control cell means having a dynamic storage node and being a means coupled to a data control line and being responsive to a decoded first clock signal for that column to set a data sense linE to a logic state opposite the logic state of its said storage node, and responsive to a decoded second clock signal for that column for setting the state of said data sense line into said storage node; a plurality of buffer means, each said buffer means being a means for receiving a plurality of address logic signals and presenting, as outputs thereof, the equivalent MOS compatible logic signals and the inverse thereof; a plurality of X decoder means, each said X decoder means being associated with a row of said memory cell means and being a means for receiving a unique combination of outputs from a first group of said buffer means and for coupling said data sense line for that row to a read output line following the occurrence of a specific and unique combination of inputs to said first group of buffer means; a plurality of Y decoder means, each said Y decoder means being associated with a column of said memory cell means and said data control cell in said column, and being a means for receiving a unique combination of outputs from a second group of said buffer means and for coupling said first clock signal and said second clock signal, as said decoded first clock signal and said decoded second clock signal, to all said cells in the respective column following the occurrence of a specific and unique combination of inputs to said second combination of buffer means; and sensing means for sensing the states of said read output line and said data control line and for providing a logic data output signal which is a first logic state signal when said read output line and said data control line is in the same state, and is a second logic state when said read output line and said data control line are in opposite states.
Claim 25
Dependent Claim
187 words
The memory of claim 20 further comprised of a read/write generator means and a write driver means, said read/write generator being coupled to said plurality of X decoder means and being a means for receiving a read/write logic signal and for providing a write command signal to said X decoder means upon the occurrence of said write logic signal, said write driver means being a means for receiving a data input logic signal and a signal from said data control line and for providing a write driver signal to said plurality of X decoder means, upon the occurrence of a timing signal, having one logic state when said data input logic signal and said data control line are at the same state, and another logic state when said data input logic signal and said data control line are in opposite states, each said X decoder means further being a means for coupling said write driver signal to said data sense line upon the occurrence of said write command signal following said occurrence of a specific and unique combination of inputs to said first combination of buffer means.
Claim 26
Dependent Claim
145 words
The memory of claim 20 further comprised of a voltage source means, said voltage source means being a means for providing an output voltage different from a predetermined voltage between the first and second voltages characteristic of predetermined logic states by an amount substantially equal to the threshold voltage of the MOS devices of said semiconductor memory, at least one of said means receiving a logic input signal having, as an input device, a first MOS device having a first and second region and an insulated gate, said first region being coupled to said output voltage of said voltage source means and said gate of said first MOS device being coupled to said logic input signal, whereby the voltage of said voltage source may compensate for threshold voltage variations in said MOS device to maintain the compatibility of the circuit receiving said logic input signal.
Claim 27
Dependent Claim
75 words
The memory of claim 22 wherein said voltage source is comprised of a second MOS device having first and second regions and an insulated gate, said second MOS device having its said first region coupled to a first power supply terminal, its said second region providing saiD output voltage of said voltage source and being coupled to said second power supply terminal through said load device, and its said gate coupled to a predetermined voltage.
Claim 28
Dependent Claim
122 words
The memory of claim 23 further comprised of a third MOS device and said load device is a fourth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said third MOS device by being coupled to said second region of said third MOS device, said gate and said first region of said third MOS device being coupled to said first power supply terminal, said fourth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 29
Dependent Claim
98 words
The memory of claim 23 further comprised of thrid and fourth MOS devices each having first and second regions and a gate, said first region of said third MOS device and said gates of said third and fourth MOS devices being coupled to a first power supply terminal, said second region of said third MOS device being coupled to said first region of said fourth MOS device device and to said gate of said second device to provide said predetermined voltage thereto, said second region of said fourth MOS device being coupled to said second power supply terminal.
Claim 30
Dependent Claim
122 words
The memory of claim 23 further comprised of a fifth MOS device and said load device is a sixth MOS device, each having first and second regions and an insulated gate, said first region of said second MOS device being coupled to said first power supply terminal through said fifth MOS device by being coupled to said second region of said fifth MOS device, said gate and said first region of said fifth MOS device being coupled to said first power supply terminal, said sixth MOS device having its said first region and its said gate coupled to said second region and said first region of said second MOS device respectively, and its said second region to a reference power supply voltage.
Claim 31
Dependent Claim
75 words
The memory of claim 20 wherein said sensing means is comprised of first and second MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device, and said second MOS device having its said second region coupled to said gate of said first MOS device.
Claim 32
Dependent Claim
74 words
The memory of claim 27 further comprised of a coupling means, and means for simultaneously applying a first signal to said gate of said first MOS device responsive to the state of the one of said data control cells in an addressed column, and a second signal to said gate of said second MOS device responsive to the state of the one of said memory cells in an addressed column and an addressed row.
Claim 33
Dependent Claim
70 words
The memory of claim 20 further comprised of trigger means coupled to said read output line, said trigger means being a means for the sensing of the change of state of said read output line from a first state toward a second state and to provide a drive voltage to said read output line upon said sensing of the change to drive said read output line toward said second state.
Claim 34
Dependent Claim
76 words
The memory of claim 21 wherein said write driver means is comprised of first and second MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled together, said first MOS device having its second region coupled to said gate of said second MOS device, and said second MOS device having its said second region coupled to said gate of said first MOS device.
Claim 35
Dependent Claim
65 words
The memory of claim 30 further comprised of a coupling means, and means for simultaneously applying a first signal to said gate of said first MOS device responsive To the state of the one of said data control cells in an addressed column, and a second signal to said gate of said second MOS device responsive to the state of said data input logic signal.
Claim 36
Dependent Claim
157 words
The memory of claim 20 further comprised of a delay means and coupling means, and wherein said X decoder means is a means for receiving a unique combination of outputs from a first group of said buffer means and for coupling said data sense line for that row to read output line following the occurrence of a specific and unique combination of inputs to said first group of buffer means, and upon the occurrence of a delayed clock signal, the output of said delay means being coupled to said X decoder means through said coupling means, said delay means being an additional cell means having a dynamic storage node and being responsive to said first clock signal to set said output of said delay means to a logic state opposite the logic state of its said storage node, and responsive to said second clock signal for setting the state of its said output into said storage node.
References Cited (Backward Citations)
US3731287A
Cited
USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1977-11-11 | 1978-05-13 | 1978-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-11 | 1982-05-13 | 1982-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-11 | 1986-05-13 | 1986-11-12 | $7700.00 | Window Closed / Lapsed |