Address buffer circuit for semiconductor memory

Claim 2

An input buffer circuit for an address input of a semiconductor memory device, comprising: a pair of driver transistors substantially unbalanced in size and characteristic, each driver transistor having a control electrode and two output electrodes, the driver transistors being cross coupled by connection of the control electrode of each to an output electrode of the other, a pair of load transistors, one for each of the driver transistors, the load transistors being substantially balanced in size and characteristic, each of the load transistors being connected in series with one of the driver transistors and a supply voltage, means connected to turn on the pair of load transistors at a given time and to turn off the load transistors after a preselected period; means to short output electrodes of the pair of cross coupled driver transistors together to equalize the voltages on such output electrodes prior to said given time; means connected to one of the output electrodes of one of said pair of cross-coupled driver transistors to couple said one of the output electrodes to a reference potential when said address input is present during said preselected period; and a pair of address signal output circuits, each of which has an input connected to an output electrode of a different one of the pair of cross-coupled driver transistors and responsive to the voltage level thereof during said preselected period but delayed by a specified period after said given time, one of the pair of address signal output circuits producing an address signal and the other producing the complement of the address signal during a period of time beginning after said specified period.

Claim 3

An input buffer circuit according to claim 1 wherein the output electrodes of each of said pair of cross-coupled driver transistors are source and drain electrodes and the control electrode is a gate, and the drain electrode of each is directly coupled to the gate of the other.

Claim 4

An input buffer circuit according to claim 2 wherein each of the pair of load transistors has a source, a drain and a gate, and the source of each is directly connected to the drain electrode of a different one of the pair of cross-coupled driver transistors.

Claim 5

An input buffer circuit according to claim 3 wherein the gates of the pair of load transistors are both connected to first pulse generating means, and the drains of the pair of load transistors are each connected to a supply voltage source.

Claim 6

An input buffer circuit according to claim 4 wherein the first pulse generating means provides recurring pulses which are active for said preselected period beginning at said given time during each cycle of recurrence.

Claim 7

An input buffer circuit according to claim 5 wherein the means to short the output electrodes of the cross-coupled driver transistors comprises an MOS transistor having a source-drain path connected between the drain electrode of one of the pair of cross-coupled driver transistors and the drain electrode of the other of the pair, and having a gate connected to a source of recurring pulses which terminate at about said given time during each cycle of recurrence.

Claim 8

An input buffer circuit according to claim 6 wherein the means to couple said one output electrode of one of the pair of cross-coupled driver transistors to a reference potential comprises two MOS transistors having their source-drain paths connected in a series path between the drain of one of the pair of cross-coupled driver transistors and reference potential.

Claim 9

An input buffer circuit according to claim 7 wherein one of the two MOS transistors has its gate connected to address input terminal; and the other of the two has its gate connected to a source of recurring pulses which are active beginning at about said given time during each cycle of recurrence.

Claim 10

An input buffer circuit according to claim 8 wherein said one of the two MOS transistors exhibits a capacitance of a given magnitude, and the address input terminal is coupled to the drain of the other of said pair of cross-coupled driver transistors by capacitive means of substantially the same magnitude as that of said one of the two MOS transistors.

Claim 11

An input buffer circuit according to claim 6 wherein the pair of address signal output circuits each comprises first, second and third MOS transistors each of which has a source, a drain and a gate, the source-drain paths of the first and second transistors being connected in series between a supply line and a reference potential and the source-drain path of the third transistor being connected in parallel with the source-drain path of the second transistor.

Claim 12

An input buffer circuit according to claim 10 wherein the input of each of the address signal output circuits comprises a connection from the drain of a different one of the pair of cross-coupled driver transistors to the gate of the first transistor in one of the output circuits and to the gate of the second transistor in the other of the output circuits.

Claim 13

An input buffer circuit according to claim 11 wherein the gates of the third transistors in each of the output circuits are both connected to said source of recurring pulses which terminate at about said given time during each cycle of recurrence.

Claim 14

An input buffer circuit according to claim 12 wherein said supply line is connected to said supply voltage source through the source-drain path of an MOS transistor which has its gate connected to a source of recurring pulses which are active during a period of time beginning after said specified period in each cycle of recurrence.

Claim 15

An input buffer circuit according to claim 13 wherein the address signal and the complement of the address signal are produced at the node between the first and second MOS transistors in the pair of address signal output circuits.

Claim 16

An input buffer circuit according to claim 14 wherein means, having an input connected to receive the address signal and the complement of the address signal and having an output coupled to said first pulse generating means, is operative to terminate said recurring pulses after said preselected period.

Claim 17

An input buffer circuit according to claim 1 wherein feedback means responsive to the occurence of the address signal and the complement of the address signal from the address signal output circuits produces an input to the means connected to turn on and turn off the pair of load transistors.

Claim 18

An input buffer circuit according to claim 1 wherein the means connected to turn on and turn off the pair of load transistors is responsive to the operation of the address signal output circuits.

Claim 19

An input buffer circuit according to claim 1 wherein means connected to turn off the load transistors after a preselected period is responsive to the occurence of an address signal at said address signal output circuit.

Claim 20

An input latch for a semiconductor integrated circuit of the type employing insulated gate field effect transistors, comprising: a pair of driver transistors unbalanced in characteristic, each driver transistor having a source-drain path and a gate, a pair of load transistors each having a source-drain path and a gate, means connecting the source-drain path of each of the driver transistors in series with the source-drain path of a different one of the load transistors and connecting each series-connected driver and load transistor across supply voltage means, a pair of output nodes, one between each of the series-connected source-drain paths of the driver and load transistors, cross-coupling means connecting each output node to the gate of the other driver transistor, means connected to the gates of the load transistors to turn on the load transistors at a first selected time in an operating cycle, but to turn off the load transistors at a second selected time, means connected to the pair of output nodes to equalize the voltages thereon prior to said first selected time in an operating cycle, means connected to one of the output nodes to couple such node to a reference potential when an input signal is present at a time beginning at said first selected time in an operating cycle, signal output circuit means having input means coupled to at least one of the output nodes and responsive to the voltage thereon beginning at a third selected time which is after the first selected time but prior to the second selected time in an operating cycle, the signal output circuit means producing a signal during a period of time beginning after said third selected time during an operating cycle.

Claim 21

An input latch for a semiconductor integrated circuit of the type employing insulated gate field effect transistors, comprising: a pair of driver transistors unbalanced in characteristic, each driver transistor having a source-drain path and a gate, a pair of load transistors each having a source-drain path and a gate, means connecting the source-drain path of each of the driver transistors in series with the source-drain path of a different one of the load transistors and connecting each series-connected driver and load transistor across supply voltage means, a pair of output nodes, one between each of the series-connected source-drain paths of the driver and load transistors, cross-coupling means connecting each output node to the gate of the other driver transistor, means connected to the gates of the load transistors to turn on the load transistors at a first selected time in an operating cycle, but to turn off the load transistors at a second selected time, means connected to the pair of output nodes to equalize the voltages thereon prior to said first selected time in an operating cycle, means connected to one of the output nodes to couple such node to a reference potential when an input signal is present at a time beginning at said first selected time in an operating cycle, signal output circuit means having input means coupled to at least one of the output nodes and responsive to the voltage thereon beginning at a third selected time which is after the first selected time but prior to the second selected time in an operating cycle, the signal output circuit means producing a signal during a period of time beginning after said third selected time during an operating cycle.

Claim 22

An input latch according to claim 19 wherein the second selected time is determined by and occurs after the third selected time.

Claim 23

An input latch according to claim 19 wherein the means connected to the gates of the load transistors operates to cut off the load transistors in response to the occurence of the signal produced by the signal output circuit means.