US3909631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pre-charge voltage generating system
Assignee: Texas Instruments Inc
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Filing: 1973-08-02
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Granted: 1975-09-30
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Expires: 1993-08-02
Abstract
Abstract The disclosure relates to a precharge voltage generator for use in an MOS memory matrix device wherein a voltage is generated which is midway between the voltage stored designating a logical 1 and a logical 0. This voltage is constantly variable to track changes in VDD and VT during circuit operation to provide the desired midvoltage level and thereby allow accurate recognition of logic levels.
Inventors
- 👤 Norishisa Kitagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/402; G11C11/403; G11C11/404; G11C11/4094; G11C11/4096; G11C11/4099; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
A memory array having a precharge voltage generating system comprising, in combination: a. first and second precharge voltage output terminals, b. means for providing first and second periodic timing signals synchronized with timing of access to the memory array, the first and second timing signals being displaced in phase from one another, c. a source of voltage and a source of reference potential, d. means responsive to said first timing signal for coupling the source of voltage to said first output terminal, e. means responsive to said first timing signal to couple the reference potential to said second terminals, and f. means responsive to the second timing signal to couple the first and second output terminals to one another whereby both such terminals then exhibit an output voltage substantially the average of the source of voltage and the reference potential.
Claim 2
Dependent Claim
140 words
A memory array having a precharge voltage generating system comprising, in combination: a. first and second precharge voltage output terminals, b. means for providing first and second periodic timing signals synchronized with timing of access to the memory array, the first and second timing signals being displaced in phase from one another, c. a source of voltage and a source of reference potential, d. means responsive to said first timing signal for coupling the source of voltage to said first output terminal, e. means responsive to said first timing signal to couple the reference potential to said second terminals, and f. means responsive to the second timing signal to couple the first and second output terminals to one another whereby both such terminals then exhibit an output voltage substantially the average of the source of voltage and the reference potential.
Claim 3
Dependent Claim
31 words
A system as set forth in claim 1 further including a transistor and means responsive to the threshold voltage of said transistor for altering said source of voltage in relation thereto.
Claim 4
Dependent Claim
44 words
A system according to claim 2 wherein the source of voltage bears a fixed relation to a supply voltage for the memory array so that said output voltage is responsive to the value of the supply voltage and the value of the threshold voltage.
Claim 5
Dependent Claim
54 words
A system according to claim 1 wherein a third periodic timing signal is provided which occurs during the second timing signal but has a leading edge occurring a significant time after that of the second timing signal, and means are provided responsive to the third timing signal for discharging both of the output terminals.
Claim 6
Dependent Claim
24 words
A system according to claim 4 wherein the means responsive to the first, second and third timing signals are insulated gate field effect transistors.
References Cited (Backward Citations)
US3555307A
Cited
US3636530A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |