Flip-flop

Claim 2

A flip-flop, comprising first and second switching stages including: first and second insulated gate field effect transistors serving as switching elements, the inputs and outputs of said two switching stages being cross coupled to each other so that said two switching stages constitute a bistable switching circuit; first and second steering gate circuits connected with said first and second switching stages, respectively, to sense the switching states of said switching stages, said first gate circuit being constituted by a third insulated gate field effect transistor having a channel of a first conductivity type and a fourth insulated gate field effect transistor having a channel of a second conductivity type which is connected in series with said third transistor, said second gate circuit being formed by a fifth insulated gate field effect transistor having a channel of the first conductivity type and a sixth insulated gate field effect transistor having a channel of the second conductivity type which is connected in series with said fifth transistor; first and second switching circuit means for changing said switching states of said switching stages from one stable switching state sensed by the steering gate circuits to the other stable switching state, said first switching means being connected with said first switching stage and said first steering gate circuit, said second switching means being connected with said second switching stage and said second steering gate circuit; input terminals connected with said third and fifth insulated gate field effect transistors and said first and second switching circuits; means for connecting the output of the first switching stage to the gate of said sixth transistor; and means for connecting the output of the second switching means to the gate of said fourth transistor.

Claim 3

A flip-flop as set forth in claim 1, wherein said third and fifth insulated gate field effect transistors are of N-channel enhancement mode, and said fourth and sixth insulated gate field effect transistors are of P-channel enhancement mode.

Claim 4

A flip-flop, comprising a first insulated gate-type field effect transistor of a first conductivity type having the drain thereof connected with a DC power source through a first resistance element and the source thereof connected with a reference potential source; a second insulated gate type of the first conductivity type having the drain thereof connected with the gate of said first field effect transistor and with the DC power source through a second resistance element, the gate and source of said second field effect transistor being connected with the drain of said first field effect transistor and said reference potential source respectively; a third insulated gate-type field effect transistor of second condUctivity type having the source thereof connected with the drain of said first field effect transistor and the gate thereof connected with a pulse input terminal; a fourth insulated gate field effect transistor of the second conductivity type having the source thereof connected with the drain of said second field effect transistor and the gate thereof connected with said pulse input terminal; a fifth insulated gate field effect transistor of the first conductivity type having the drain thereof connected with the drain of said third field effect transistor and the gate thereof connected with the drain of said second field effect transistor and the source thereof connected with the reference potential source; a sixth field effect transistor of the first conductivity type the drain, source and gate of which are connected with the drain of said fourth field effect transistor, said reference potential source and the drain of said first field effect transistor respectively; a seventh insulated gate field effect transitor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said first field effect transistor through the passage between the source and the drain of a control insulated gate field effect transistor of the first conductivity type, the gate of said seventh transistor being connected with the drain of said fifth field effect transistor; and an eighth insulated gate field effect transistor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said second field effect transistor through the passage between the source and the drain of said control insulated gate field effect transistor being connected with the drain of said sixth field effect transistor, the gate of said control field effect transistor being connected with said pulse input terminal.

Claim 5

A flip-flop, comprising a first insulated gate-type field effect transistor of a first conductivity type having the drain thereof connected with a DC power source through a first resistance element and the source thereof connected with a reference potential source; a second insulated gate type of the first conductivity type having the drain thereof connected with the gate of said first field effect transistor and with the DC power source through a second resistance element, the gate and source of said second field effect transistor being connected with the drain of said first field effect transistor and said reference potential source respectively; a third insulated gate-type field effect transistor of second condUctivity type having the source thereof connected with the drain of said first field effect transistor and the gate thereof connected with a pulse input terminal; a fourth insulated gate field effect transistor of the second conductivity type having the source thereof connected with the drain of said second field effect transistor and the gate thereof connected with said pulse input terminal; a fifth insulated gate field effect transistor of the first conductivity type having the drain thereof connected with the drain of said third field effect transistor and the gate thereof connected with the drain of said second field effect transistor and the source thereof connected with the reference potential source; a sixth field effect transistor of the first conductivity type the drain, source and gate of which are connected with the drain of said fourth field effect transistor, said reference potential source and the drain of said first field effect transistor respectively; a seventh insulated gate field effect transitor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said first field effect transistor through the passage between the source and the drain of a control insulated gate field effect transistor of the first conductivity type, the gate of said seventh transistor being connected with the drain of said fifth field effect transistor; and an eighth insulated gate field effect transistor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said second field effect transistor through the passage between the source and the drain of said control insulated gate field effect transistor being connected with the drain of said sixth field effect transistor, the gate of said control field effect transistor being connected with said pulse input terminal.

Claim 6

A flip-flop as set forth in claim 3, wherein first and second insulated gate field effect transistors of the first conductivity type are used instead of said control transistor, the passage between the source and the drain of said first control field effect transistor is connected in series with that of said seventh transistor, the passage between the source and the drain of said second control field effect transistor is connected in series with that of said eighth transistor, and the gates of said first and second control transistors are connected with said pulse input terminal.

Claim 7

A flip-flop as set forth in claim 3, wherein insulated gate field effect transistors are utilized as said first and second resistance elements.