US4074148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address buffer circuit in semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1976-06-03
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Granted: 1978-02-14
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Expires: 1996-06-03
Abstract
Abstract In an address buffer circuit in a semiconductor memory including a flip-flop formed of MISFETs and an output circuit consisting of two drivers each formed of MISFETs, and producing a binary address signal, the flip-flop is supplied with a constant operating voltage and triggered by a pulse signal of shorter pulse width than that of a chip enable signal and the MISFETs of the driver on the ground side have the gates cross-coupled to the outputs of the respective drivers so that at least one grounding MISFET in each driver is turned on in the outputting period to prevent the floating of the output level.
Inventors
- 👤 Takashi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; G11C11/41; G11C11/413; G11C11/417; G11C11/418
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
192 words
An address buffer circuit for a semiconductor memory circuit comprising: a dynamic flip-flop circuit operated by an operating voltage and including first and second inverters and voltage-driven load means series-connected to the respective inverters, an input node of each inverter being cross-coupled with an output node of the other inverter, said flip-flop circuit receiving an input signal at the input node of said second inverter and providing mutually opposite output signals at the output nodes of said first and second inverters respectively upon application of a driving pulse signal to said load means to couple said inverters to the operating voltage, an output circuit including first and second drivers connected to receive the output signals of the flip-flop circuit respectively from the output nodes of said second and first inverters and providing mutually opposite pulse outputs of the buffer circuit, and driving pulse generating means coupled to control terminals of said load means for generating a driving pulse signal existing for a period between the occurrence of a control signal of the memory circuit and that of a pulse output at said output circuit and driving said load means in conduction thereby.
Claim 2
Dependent Claim
192 words
An address buffer circuit for a semiconductor memory circuit comprising: a dynamic flip-flop circuit operated by an operating voltage and including first and second inverters and voltage-driven load means series-connected to the respective inverters, an input node of each inverter being cross-coupled with an output node of the other inverter, said flip-flop circuit receiving an input signal at the input node of said second inverter and providing mutually opposite output signals at the output nodes of said first and second inverters respectively upon application of a driving pulse signal to said load means to couple said inverters to the operating voltage, an output circuit including first and second drivers connected to receive the output signals of the flip-flop circuit respectively from the output nodes of said second and first inverters and providing mutually opposite pulse outputs of the buffer circuit, and driving pulse generating means coupled to control terminals of said load means for generating a driving pulse signal existing for a period between the occurrence of a control signal of the memory circuit and that of a pulse output at said output circuit and driving said load means in conduction thereby.
Claim 3
Dependent Claim
87 words
The address buffer circuit according to claim 1, wherein each of said first and second inverters with said load means comprises a series connection of metal-insulator-semiconductor field effect transistors (MISFETs), said first and second inverters are connected to a voltage source supplying a constant operating voltage at least in the presence of said driving pulse, and each of said first and second drivers comprises a series connection of MISFETs whose junction is connected to a respective one of a pair of output terminals of said output circuit.
Claim 4
Dependent Claim
101 words
The address buffer circuit according to claim 2, wherein the series-connected MISFETs constituting each of said first and second drivers are connected between a terminal for supplying the constant operating voltage at least during the presence of said driving pulse signal and a terminal of a reference potential, and the outputs of said first and second drivers are cross-coupled to the gates of the MISFETs of the drivers which are connected to the reference potential terminal, so as to maintain the output of one of said drivers at the reference potential whenever an output signal is generated at the other driver.
Claim 5
Dependent Claim
53 words
The address buffer circuit according to claim 3, wherein another MISFET is connected in parallel to the MISFET of each of said inverters and drivers connected to the reference potential and has a gate applied with another control signal having a phase inverted with respect to said control signal of the memory circuit.
Claim 6
Dependent Claim
72 words
The address buffer circuit according to claim 2, wherein the input signal is applied to the flip-flop circuit through a series connection of two MISFETs, one of which has a gate applied with said control signal and the other of which has a gate applied with an address signal, and inputs of said drivers are cross-fed to the gates of those MISFETs of the drivers which are connected to a reference potential.
Claim 7
Dependent Claim
78 words
The address buffer circuit according to claim 1, wherein said driving pulse generating means comprises an input terminal for receiving said control signal, a ground level terminal, an output terminal for providing an output signal having a voltage level substantially equal to that of said control signal in synchronism with said control signal, and means for short-circuiting the output terminal to the ground level upon application of any output signal from the output circuit of said buffer circuit.
Claim 8
Dependent Claim
181 words
An address buffer circuit for a semiconductor memory comprising: an MIS flip-flop circuit operated by an operating voltage and including first and second inverters formed of MISFETs, each of said inverters having an input node applied with an input signal and an output node providing the output of the flip-flop, the input node of each inverter being cross-coupled with the output node of the other inverter; first and second driver circuits responsive to the outputs of said flip-flop circuit for providing a pair of outputs of the buffer circuit, each driver circuit including a series connection of first and second MISFETs connected to said operating voltage and a reference potential respectively and the node between the series-connected MISFETs serving as one of the pair of the outputs of the buffer circuit; said first MISFETs of the driver circuits having gates connected to the output nodes of said first and second inverters of the flip-flop circuit respectively, and said second MISFETs of the first and second driver circuits having gates cross-coupled to the output nodes of said first and second driver circuits.
Claim 9
Dependent Claim
181 words
An address buffer circuit for a semiconductor memory comprising: an MIS flip-flop circuit operated by an operating voltage and including first and second inverters formed of MISFETs, each of said inverters having an input node applied with an input signal and an output node providing the output of the flip-flop, the input node of each inverter being cross-coupled with the output node of the other inverter; first and second driver circuits responsive to the outputs of said flip-flop circuit for providing a pair of outputs of the buffer circuit, each driver circuit including a series connection of first and second MISFETs connected to said operating voltage and a reference potential respectively and the node between the series-connected MISFETs serving as one of the pair of the outputs of the buffer circuit; said first MISFETs of the driver circuits having gates connected to the output nodes of said first and second inverters of the flip-flop circuit respectively, and said second MISFETs of the first and second driver circuits having gates cross-coupled to the output nodes of said first and second driver circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-13 | 1981-08-15 | 1982-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-13 | 1985-08-15 | 1986-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-13 | 1989-08-15 | 1990-02-14 | $7700.00 | Window Closed / Lapsed |