US4055754A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory device and method of testing the same
Assignee: Individual
•
Filing: 1975-12-22
•
Granted: 1977-10-25
•
Expires: 1995-12-22
Abstract
Abstract Integrated circuit memory device and method of testing the same wherein test logic is included in the device for detecting the presence of predetermined patterns applied to the memory cells. The cells are tested in groups to reduce the amount of time required for the test.
Inventors
- 👤 Gilman D. Chesley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4078; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/38
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
130 words
In an integrated circuit memory device: a plurality of memory cells, means for writing data into and reading data out of the memory cells, first coincidence gate means responsive to data read simultaneously out of a group of the memory cells for determining whether all of the group is of a first logic level, second coincidence gate means responsive to data read simultaneously out of the group of cells for determining whether all the data from said group is of a second logic level, and output gate means responsive to the outputs of the first and second coincidence gate means for delivering an output signal when the data read out of the group of cells is either all of the first logic level or all of the second logic level.
Claim 2
Dependent Claim
130 words
In an integrated circuit memory device: a plurality of memory cells, means for writing data into and reading data out of the memory cells, first coincidence gate means responsive to data read simultaneously out of a group of the memory cells for determining whether all of the group is of a first logic level, second coincidence gate means responsive to data read simultaneously out of the group of cells for determining whether all the data from said group is of a second logic level, and output gate means responsive to the outputs of the first and second coincidence gate means for delivering an output signal when the data read out of the group of cells is either all of the first logic level or all of the second logic level.
Claim 3
Dependent Claim
34 words
The memory device of claim 1 further including inverter means connected between the memory cells and the gate means for selectively inverting the data read out of one of the cells in the group.
Claim 4
Dependent Claim
34 words
The memory device of claim 1 wherein the first coincidence gate means comprises an AND gate, the second coincidence gate means comprises a NAND gate, and the output gate means comprises an OR gate.
References Cited (Backward Citations)
US3644899A
Cited
US3659088A
Cited
US3751649A
Cited
US3815025A
Cited
US3873818A
Cited
USB483268I5
Cited
US3961252A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-24 | 1981-04-25 | 1981-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-24 | 1985-04-25 | 1985-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-24 | 1989-04-25 | 1989-10-25 | $7700.00 | Window Closed / Lapsed |