US3659088A
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US
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Method for indicating memory chip failure modes
Assignee: Cogar Corp
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Filing: 1970-08-06
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Granted: 1972-04-25
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Expires: 1990-08-06
Abstract
Abstract A machine-practiced method for indicating memory chip failure modes. The individual memory cells on a chip are tested in accordance with standard practice. Each test has associated with it a respective one of the binary numbers 1, 2, 4, 8,.... An ''''error syndrome'''' is provided for each cell, and when that cell fails a particular test the respective binary number is added to the error syndrome for the cell. At the end of the sequence a chip map is printed. For each cell there is printed the respective error syndrome; that number identifies a particular group of tests which have been failed by the cell. By analyzing the error syndromes it is possible to identify individual cell failures, group cell failures and gross (total chip) failures. Moreover, the technique of the invention is a valuable diagnostic aid because it enables the causes of many failures to be ascertained.
Inventors
- 👤 Conrad J Boisvert Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:54
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/10
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
78 words
A machine-practiced method for indicating memory chip failure modes comprising the steps of: 1. performing a series of electronic tests on each of the cells on a chip, 2. assigning different binary numbers to each of said tests, 3. forming an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell, and 4. providing a record of the error syndrome numbers for all cells.
Claim 2
Dependent Claim
78 words
A machine-practiced method for indicating memory chip failure modes comprising the steps of: 1. performing a series of electronic tests on each of the cells on a chip, 2. assigning different binary numbers to each of said tests, 3. forming an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell, and 4. providing a record of the error syndrome numbers for all cells.
Claim 3
Dependent Claim
9 words
assigning different binary numbers to each of said tests,
Claim 4
Dependent Claim
9 words
assigning different binary numbers to each of said tests,
Claim 5
Dependent Claim
9 words
assigning different binary numbers to each of said tests,
Claim 6
Dependent Claim
9 words
assigning different binary numbers to each of said tests,
Claim 7
Dependent Claim
12 words
assigning different numbers to each of the tests performed on the cells,
Claim 8
Dependent Claim
12 words
assigning different numbers to each of the tests performed on the cells,
Claim 9
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the cells, and
Claim 10
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the cells, and
Claim 11
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the circuits, and
Claim 12
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the circuits, and
Claim 13
Dependent Claim
42 words
A machine-practiced method for indicating memory chip failure modes in accordance with claim 1 wherein in step (4) the error syndrome numbers are printed on a chip map having a format corresponding to the physical lay-out of the cells on the chip.
Claim 14
Dependent Claim
36 words
deriving an error syndrome symbol for the circuit which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 15
Dependent Claim
36 words
deriving an error syndrome symbol for the circuit which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 16
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the circuit, and,
Claim 17
Dependent Claim
13 words
assigning different numbers to each of the tests performed on the circuit, and,
Claim 18
Dependent Claim
42 words
forming an error syndrome number for the circuit which is a function of the numbers assigned to each of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome number.
Claim 19
Dependent Claim
42 words
forming an error syndrome number for the circuit which is a function of the numbers assigned to each of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome number.
Claim 20
Dependent Claim
123 words
A machine-practiced method for indicating memory chip failure modes in accordance with claim 1 wherein the chip includes a 0 sense line and a 1 sense line and a cell is tested by examining the signal on one of the 0 and 1 sense lines, steps (1) and (3) are performed twice for each cell with an error syndrome number being formed in step (3) for each of the 0 and 1 sense lines when each cell is tested, and in step (4) two chip maps are printed each containing the error syndrome numbers associated with respective cells when respective 0 and 1 sense lines are examined and each having a format corresponding to the physical lay-out of the cells on the chip.
Claim 21
Dependent Claim
42 words
forming an error syndrome number for each circuit which is a function of the numbers assigned to each of the tests failed by the circuit such that every combination of tests failures results in the formation of a unique error syndrome number.
Claim 22
Dependent Claim
42 words
forming an error syndrome number for each circuit which is a function of the numbers assigned to each of the tests failed by the circuit such that every combination of tests failures results in the formation of a unique error syndrome number.
Claim 23
Dependent Claim
42 words
forming an error syndrome number for each cell which is a function of the numbers assigned to each of the tests failed by the cell such that every combination of test failures results in the formation of a unique error syndrome number.
Claim 24
Dependent Claim
42 words
forming an error syndrome number for each cell which is a function of the numbers assigned to each of the tests failed by the cell such that every combination of test failures results in the formation of a unique error syndrome number.
Claim 25
Dependent Claim
43 words
forming an error syndrome number for each cell which is a function of the numbers assigned to each of the tests failed by the cell such that every combination of test failures results in the formation of a unique error syndrome number, and
Claim 26
Dependent Claim
43 words
forming an error syndrome number for each cell which is a function of the numbers assigned to each of the tests failed by the cell such that every combination of test failures results in the formation of a unique error syndrome number, and
Claim 27
Dependent Claim
31 words
causing said automatic tester to form an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell,
Claim 28
Dependent Claim
31 words
causing said automatic tester to form an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell,
Claim 29
Dependent Claim
27 words
forming an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell, and
Claim 30
Dependent Claim
27 words
forming an error syndrome number for each cell which is the sum of the binary numbers assigned to each of the tests failed by the cell, and
Claim 31
Dependent Claim
11 words
providing a record of the error syndrome numbers for all cells.
Claim 32
Dependent Claim
11 words
providing a record of the error syndrome numbers for all cells.
Claim 33
Dependent Claim
17 words
causing said automatic tester to provide a record of the error syndrome numbers for all cells, and
Claim 34
Dependent Claim
17 words
causing said automatic tester to provide a record of the error syndrome numbers for all cells, and
Claim 35
Dependent Claim
11 words
providing a record of the error syndrome numbers for all cells.
Claim 36
Dependent Claim
11 words
providing a record of the error syndrome numbers for all cells.
Claim 37
Independent Claim
13 words
A method for determining probable memory chip failure modes comprising the steps of:
Claim 38
Independent Claim
13 words
A method for determining probable memory chip failure modes comprising the steps of:
Claim 39
Dependent Claim
12 words
identifying probable chip failure modes from the record of error syndrome numbers.
Claim 40
Dependent Claim
12 words
identifying probable chip failure modes from the record of error syndrome numbers.
Claim 41
Dependent Claim
42 words
A method for determining probable memory chip failure modes in accordance with claim 4 wherein in step (4) the error syndrome numbers are printed on a chip map having a format corresponding to the physical lay-out of the cells on the chip.
Claim 42
Dependent Claim
123 words
A method for determining probable memory chip failure modes in accordance with claim 4 wherein the chip includes a 0 sense line and a 1 sense line and a cell is tested by examining the signal on one of the 0 and 1 sense lines, steps (1) and (3) are performed twice for each cell with an error syndrome number being formed in step (3) for each of the 0 and 1 sense lines when each cell is tested, and in step (4) two chip maps are printed each containing the error syndrome numbers associated with respective cells when respective 0 and 1 sense lines are examined and each having a format corresponding to the physical lay-out of the cells on the chip.
Claim 43
Dependent Claim
14 words
A machine-practical method for indicating probable memory chip failure modes comprising the steps of:
Claim 44
Dependent Claim
14 words
A machine-practical method for indicating probable memory chip failure modes comprising the steps of:
Claim 45
Dependent Claim
43 words
A machine-practiced method for indicating probable memory chip failure modes in accordance with claim 7 wherein in step (4) the error syndrome numbers are printed on a chip may having a format corresponding to the physical lay-out of the cells on the chip.
Claim 46
Dependent Claim
124 words
A machine-practiced method for indicating probable memory chip failure modes in accordance with claim 7 wherein the chip includes a 0 sense line and a 1 sense line and a cell is tested by examining the signal on one of the 0 and 1 sense lines, steps (1) and (3) are performed twice for each cell with an error syndrome number being formed in step (3) for each of the 0 and 1 sense lines when each cell is tested, and in step (4) two chip maps are printed each containing the error syndrome numbers associated with respective cells when respective 0 and 1 sense lines are examined and each having a format corresponding to the physical lay-out of the cells on the chip.
Claim 47
Dependent Claim
14 words
A machine-practiced method for indicating probable memory chip failure modes comprising the steps of:
Claim 48
Dependent Claim
14 words
A machine-practiced method for indicating probable memory chip failure modes comprising the steps of:
Claim 49
Dependent Claim
43 words
A machine-practiced method for indicating probable memory chip failure modes in accordance with claim 10 further including the step of printing the error syndrome numbers on a chip map having a format corresponding to the physical lay-out of the cells on the chip.
Claim 50
Dependent Claim
125 words
A machine-practiced method for indicating probable memory chip failure modes in accordance with claim 10 wherein the chip includes a 0 sense line and a 1 sense line and a cell is tested by examining the signal on one of the 0 and 1 sense lines, steps (1) and (3) are performed twice for each cell with an error syndrome number being formed in step (3) for each of the 0 and 1 sense lines when each cell is tested, and further including the step of printing two chip maps each containing the error syndrome numbers associated with respective cells when respective 0 and 1 sense lines are examined and each having a format corresponding to the physical lay-out of the cells on the chip.
Claim 51
Dependent Claim
13 words
A machine-practiced method for indicating probable chip failure modes comprising the steps of:
Claim 52
Dependent Claim
13 words
A machine-practiced method for indicating probable chip failure modes comprising the steps of:
Claim 53
Dependent Claim
42 words
A machine-practiced method for indicating probable chip failure modes in accordance with claim 13 further including the step of printing the error syndrome numbers on a chip map having a format corresponding to the physical lay-out of the circuits on the chip.
Claim 54
Independent Claim
72 words
A method for aiding the diagnosis of chip failure modes for a chip having a plurality of circuits on which a number of electronic tests have been performed comprising the step of: forming an error syndrome symbol for at least one of said circuits which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 55
Independent Claim
72 words
A method for aiding the diagnosis of chip failure modes for a chip having a plurality of circuits on which a number of electronic tests have been performed comprising the step of: forming an error syndrome symbol for at least one of said circuits which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 56
Independent Claim
61 words
A method for aiding the diagnosis of a circuit failure mode for a circuit having failed a number of electronic tests comprising the step of: deriving an error syndrome symbol for the circUit which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 57
Independent Claim
61 words
A method for aiding the diagnosis of a circuit failure mode for a circuit having failed a number of electronic tests comprising the step of: deriving an error syndrome symbol for the circUit which is a function of the tests failed by the circuit such that every combination of test failures results in the formation of a unique error syndrome symbol.
Claim 58
Independent Claim
16 words
A method for aiding in the diagnosis of a circuit failure mode comprising the steps of:
Claim 59
Independent Claim
16 words
A method for aiding in the diagnosis of a circuit failure mode comprising the steps of:
Claim 60
Dependent Claim
17 words
A machine-practiced method for aiding in the diagnosis of a circuit failure mode comprising the steps of:
Claim 61
Dependent Claim
17 words
A machine-practiced method for aiding in the diagnosis of a circuit failure mode comprising the steps of:
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-25 | 1975-10-25 | 1976-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-25 | 1979-10-25 | 1980-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-25 | 1983-10-25 | 1984-04-25 | $7700.00 | Window Closed / Lapsed |