US3815025A
Expired / Lapsed
US
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Large-scale integrated circuit testing structure
Assignee: International Business Machines Corp
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Filing: 1971-10-18
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Granted: 1974-06-04
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Expires: 1991-10-18
Abstract
Abstract A plurality of sequential logic circuits are connected to a shift register, both located on the same semiconductor chip. Input test data supplied at a chip input pad is routed via parallel paths interconnecting the sequential logic circuits to the shift register for performing combinatorial logic tests. The test responses are accessible to a chip output pad via the shift register. The shift register functions as virtual input/output pads so as to permit combinatorial logic testing on high density sequential logic circuits without increasing the actual input/output pad requirements of the semiconductor chip.
Inventors
- 👤 P Jordan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
203 words
Large-scale integrated circuit testing structure for a semiconductor chip having a plurality of input and output pads comprising: a. sequential logic circuitry means connected to at least a first chip input pad and to at least a first chip output pad for providing a logic flow of information between said first input and output pads, b. memory testing means connected to said sequential logic circuitry and including input and output terminals for receiving a data test pattern and for delivering a combinatorial output test pattern response, said memory testing means being located external to said logic flow associated with said sequential logic circuitry means, c. interconnection means connecting said sequential logic circuitry means to said memory means for selectively applying a data test pattern stored in said memory means to said sequential logic circuitry means for establishing a predetermined logic condition therein, d. said sequential logic circuitry meaNs being responsive to logic signals for generating a combinatorial output test pattern response, e. said interconnection means being further responsive for selectively transmitting the combinatorial output test pattern responses from said logic circuitry means into said memory testing means, whereby f. said memory testing means functions as virtual chip input/output pads for the semiconductor chip.
Claim 2
Dependent Claim
203 words
Large-scale integrated circuit testing structure for a semiconductor chip having a plurality of input and output pads comprising: a. sequential logic circuitry means connected to at least a first chip input pad and to at least a first chip output pad for providing a logic flow of information between said first input and output pads, b. memory testing means connected to said sequential logic circuitry and including input and output terminals for receiving a data test pattern and for delivering a combinatorial output test pattern response, said memory testing means being located external to said logic flow associated with said sequential logic circuitry means, c. interconnection means connecting said sequential logic circuitry means to said memory means for selectively applying a data test pattern stored in said memory means to said sequential logic circuitry means for establishing a predetermined logic condition therein, d. said sequential logic circuitry meaNs being responsive to logic signals for generating a combinatorial output test pattern response, e. said interconnection means being further responsive for selectively transmitting the combinatorial output test pattern responses from said logic circuitry means into said memory testing means, whereby f. said memory testing means functions as virtual chip input/output pads for the semiconductor chip.
Claim 3
Dependent Claim
50 words
Large-scale integrated circuit testing structure for a semiconductor chip having input and output pads as in claim 1 wherein: a. said sequential logic circuitry means comprises a plurality of logic elements each having input and output terminals, and b. said memory testing means comprises a plurality of shift register stages.
Claim 4
Dependent Claim
62 words
Large-scale integrated circuit testing structure for a semiconductor chip having input and output pads as in claim 2 wherein: a. said interconnection means includes first gating means connected to said logic element output terminals, b. said first gating means being selectively responsive to control signals for reading test pattern responses from said individual logic elements into said plurality of shift register stages.
Claim 5
Dependent Claim
46 words
Large-scale integrated circuit testing structure for a semiconductor chip having input and output pads including device structure as in Claim 3 further including: a. second gating means connected to said logic element input terminals for reading said data test pattern into said plurality of logic elements.
Claim 6
Dependent Claim
48 words
Large-scale integrated circuit testing structure for a semiconductor chip having input and output pads including device structure as in claim 4 wherein: a. each one of said plurality of logic elements are selectively functionally independent and interconnected to a predetermined one of said plurality of shift register stages.
Claim 7
Dependent Claim
30 words
Large-scale integrated circuit testing structure for a semiconductor chip having input and output pads including device structure as in claim 5 wherein: a. said individual logic elements comprise latch circuits.
References Cited (Backward Citations)
US3582633A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |