Electronic tester for testing devices having a high circuit density

Claim 2

An electronic test system for testing high density logic networks, said networks having n contact pins, each of said contact pins having associated therewith a function, where n is an integer having any value in the range of one hundred through five hundred, said test system employing at least one test pattern under control of a system test program, said test pattern including at least m test steps and each said test step utilizing a discrete test word having n discrete electrical manifestations of logical ones and/or logical zeros, where m is an integer having any value in the range of one hundred to one thousand, said test system including: a system controller operative under control of said test program for monitoring and controlling each test step of said test pattern, said system controller including bulk storage means for storing test data; a word oriented random access memory coupled to said system controller and having a capacity capable of storing z words of test data, where each word of test data has n discrete binary bits of test data and z is an integer less than said integer m in magnitude, said word oriented random access memory including operational code specifying means for specifying an operational code for each word of test data stored in said word oriented random access memory; n pin circuits each having at least a test data input, and an output, each of said pin circuits being settable to perform any one of a plurality of functions, each of said n outputs of said n pin circuits being connected to a discrete one of said n contact pins of a network under test; a closed loop high speed shift register having n stages, each stage of said shift register having at least an input coupled to a particular binary bit position of each of said z word storage positions of said word oriented random access memory, and an output coupled to a predetermined one of said n test data inputs of said n pin circuits; decode circuitry intercoupling said system controller, said operational code specifying means, said shift register and each of said n pin circuits, said decode circuitry being adapted to, during each test step, in response to an input from said operational code specifying means, and under control of said system controller, selectively control at least each of said n pin circuits and said shift register, whereby during each of said m test steps an n bit binary word is impressed on said n contact pins of a network under test, and whereby said word oriented random access memory contains in said z word storage positions thereof all of the test data required to subject a network under test to a test pattern having m test words.

Claim 3

An electronic test system in accordance with claim 1 wherein said word oriented random access memory is a solid-state device, said operational code specifying means has the capacity to store a discrete manifestation of an operational code for each test data word, and each said operational code is manifested by a plurality of operational code specifying binary bits.

Claim 4

An electronic test system in accordance with claim 2 wherein said decode circuitry comprises circuit means including logical circuit means for receiving said operational code specifying binary bits and at least one timing signal from said system controller, said circuit means including means for electrically manifesting to each of said n pin circuits and said shift register at least certain operations called for by said operational code specifying binary bits.

Claim 5

An electronic test system in accordance with claim 1 wherein each operational code specified by said operational code specifying means is manifested by a plurality of binary bits, and where there is a discrete operational code for at least one of the following opertion: SET NUMBER OF SERIAL TESTS; SET PIN SERIAL; TEST SERIAL; TEST PARALLEL; TEST TESTER; SET CLOCK 1; SET DISCONNECT; SET-LOAD, OUT, MASK; SET-LOAD, OUT, MASK; SET-LOAD, IN, MASK; SET-LOAD,IN,MASK; SET-LOAD,OUT,MASK; SET-LOAD, OUT, MASK; SET-LOAD, IN, MASK; and, SET-LOAD, IN, MASK.

Claim 6

An electronic test system in accordance with claim 1 wherein said operational specifying means specifies each operational code by a discrete binary word having at least four binary bits whereby at least sixteen discrete binary words are available to respectively specify an operational code, and at least one or more of the following operational codes are respectively specified by a discrete one of said binary words, SET number of SERIAL TESTS, SET PIN SERIAL, TEST SERIAL and TEST PARALLEL.

Claim 7

An electronic test system as claimed in claim 5 wherein said decode circuitry includes: first circuit means for receiving said binary bits calling for a specific operational code; second circuit means adapted to receive at least one series of timing pulses from said controller and at least one input from said shift register; third circuit means intercoupling said first and second circuit means and including logic means; a first group of outputs of said decode circuitry interconnecting said third circuit means and said shift register; a second group of outputs of said decode circuitry interconnecting said third circuit means and said n pin circuits, whereby each of said n pin circuits and said shift register function in accordance with the operational codes called for by the operational code specifying bits.

Claim 8

In a test method for testing a large scale integration device having n terminals, where n is an integer having any value in the range of one hundred through five hundred, said method including m discrete test steps, each test step of said m test steps including the impressing of a discrete n binary word bit on said n terminals, where m is an integer having any value in the range of one hundred through one thousand, said method employing test apparatus including test system controller means, word oriented random access storage means, n discrete pin circuit means coupled to n pins of a device under test, and binary word assembly means, said method comprising the steps of: a. conditioning each of said n pin circuit means to perform a discrete one of a plurality of functions, where said functions include input, output, driver, load, ground and open, and said functions are in accordance with the function of the terminal of the device under test to which the pin circuit is coupled. b. obtaining during a first test step a first one of said m discrete n binary bit test words from said word oriented random access storage means, c. impressing said first test word on said n discrete pin circuit means, d. obtaining during a second test step a predetermined portion of a second one of said m discrete n binary bit test words from said word oriented random access storage means, e. utilizing said binary word assembly means to construct said second one of said m discrete n binary bit test words from said first test word and said predetermined portion of said second test word, f. impressing said second test word on said n discrete pin circuit means.

Claim 9

In a test method for testing a large scale integration device having n terminals, where n is an integer having any value in the range of one hundred through five hundred, said method including m discrete test steps, each test step of said m test steps including the impressing of a discrete n binary word bit on said n terminals, where m is an integer having any value in the range of one hundred through one thousand, said method employing test apparatus including test system controller means, word oriented random access storage means, n discrete pin circuit means coupled to n pins of a device under test, and binary word assembly means, said method comprising the steps of: a. conditioning each of said n pin circuit means to perform a discrete one of a plurality of functions, where said functions include input, output, driver, load, ground and open, and said functions are in accordance with the function of the terminal of the device under test to which the pin circuit is coupled. b. obtaining during a first test step a first one of said m discrete n binary bit test words from said word oriented random access storage means, c. impressing said first test word on said n discrete pin circuit means, d. obtaining during a second test step a predetermined portion of a second one of said m discrete n binary bit test words from said word oriented random access storage means, e. utilizing said binary word assembly means to construct said second one of said m discrete n binary bit test words from said first test word and said predetermined portion of said second test word, f. impressing said second test word on said n discrete pin circuit means.

Claim 10

In a test method as recited in claim 7 wherein during at least certain of said m test steps, subsequent to said second test step, a predetermined portion of the test word to be employed is obtained from the word oriented random access storage means and said binary word assembly means is employed to construct a discrete n binary bit test word.

Claim 11

In a test mEthod as recited in claim 8 wherein during each of said m steps a discrete n binary bit test word is impressed on said n discrete pin circuit means, and during at least certain of said test steps a determination is made as to the merit, or lack of merit of the device under test.

Claim 12

In a test method as recited in claim 9 wherein during each of said m test steps an operational code is specified by said test system controller means and where the operation of said test apparatus during each of said m test steps is in accordance with the operational code specified.

Claim 13

In a test method as recited in claim 9, wherein said large scale integration device under test comprises high density circuit means, at least one portion of said high density means, circuit requiring at least one serial input of time displaced electrical manifestations for the effective testing of said high density circuit means.

Claim 14

In a test method as recited in claim 9 wherein at least one of said n terminals of said large scale integraton device requires for effective testing of said large scale integration device the impressing of an electrical manifestation varying in time, in a prescribed manner.

Claim 15

In a test method as recited in claim 9 wherein certain of said m test steps are devoted to applying serial test data to said device under test and others of said m test steps are devoted to applying parallel test data to said device under test.

Claim 16

In a test method as recited in claim 13 wherein each of said n pin circuits means is settable to perform one of the afore-identified functions, a plurality of said pin circuit means set to perform an output function, at least one of said plurality of output pin circuit means being adapted to receive an electrical manifestation varying in time in an anticipated prescribed manner from said device under test during at least a certain consecutive number of said m test steps.

Claim 17

In a test method as recited in claim 9 wherein during the execution of certain ones of said m test steps said test apparatus is operating in a Set-UP MODE, and during other ones of said m test steps said apparatus is operating in a TEST MODE.

Claim 18

In a test method as recited in claim 15 wherein during each of said m test steps, where said test appartus is operating in the TEST MODE, a determination is made as to the merit or lack of merit of the device under test.

Claim 19

In a test method as recited in claim 15 wherein during at least one or more of said m test steps where said test apparatus is operating in the TEST MODE said test apparatus is executing a self imposed test.

Claim 20

In a test method as recited in claim 15 wherein during at least certain of said m test steps where said test apparatus is operating in the Set-UP MODE at least certain of said n Pin circuit means are set-up to perform a predetermined function.

Claim 21

An electronic tester operative under control of a computer system for testing high circuit density devices, said tester including: storage means responsive in said computer system for storing a first integer number of discrete test data words of a given length and a second integer number of selected portions of discrete data words of said given length; settable circuit means coupled to a high circuit density device under test and adapted to successively receive a test data word of said given length; word construction circuit means coupling said storage means to said settable circuit means and responsive to said computer system, said word construction circuit means being adapted to construct a third integer number of discrete test data words of said given length from said first integer number of discrete data words and said second integer number of selected portions of discrete data words, where said third integer number is equal to the sum of said first and second integer numbers; and said word construction circuit means including circuit means fOr successively impressing each of said third integer number of discrete test data words on said settable circuit means, whereby the test data storage capacity of said storage means may be less than the storage capacity required to store said third integer number of discrete test data words.

Claim 22

An electronic tester operative under control of a computer system for testing high circuit density devices, said tester including: storage means responsive in said computer system for storing a first integer number of discrete test data words of a given length and a second integer number of selected portions of discrete data words of said given length; settable circuit means coupled to a high circuit density device under test and adapted to successively receive a test data word of said given length; word construction circuit means coupling said storage means to said settable circuit means and responsive to said computer system, said word construction circuit means being adapted to construct a third integer number of discrete test data words of said given length from said first integer number of discrete data words and said second integer number of selected portions of discrete data words, where said third integer number is equal to the sum of said first and second integer numbers; and said word construction circuit means including circuit means fOr successively impressing each of said third integer number of discrete test data words on said settable circuit means, whereby the test data storage capacity of said storage means may be less than the storage capacity required to store said third integer number of discrete test data words.

Claim 23

An electronic tester for testing large scale integration devices, said devices having n contact pins, where n is an integer having a magnitude of at least one hundred, said tester being under control of a computer system, said tester comprising: a solid state word oriented random access memory responsive to said computer system, said memory having k binary word storage positions, each of said word storage positions having a binary bit positions for storing test data, and x binary bit positions for storing control data, where k is an integer having a magnitude of at least four hundred and x is an integer having a magnitude of at least four; controllable shift register means coupled to said memory and adapted to store n binary bits, said shift register means being adapted to successively receive n binary bits of test data from said memory; n pin circuits means coupled to said controllable shift register means and said n contact pins of a device under test; control means for controlling said shift register means and each of said n pin circuit means, said control means interconnecting said shift register means and said n pin circuit means, said control means cooperating with said computer system and being successively responsive to binary values obtained from said x binary bit positions of successive ones of said k binary word positions of said memory, whereby a multiple of k n binary bit words of Serial/Parallel test data may be stored in said k binary word storage positions of said word oriented random access memory.

Claim 24

An electronic tester for testing large scale integration devices, said devices having n contact pins, where n is an integer having a magnitude of at least one hundred, said tester being under control of a computer system, said tester comprising: a solid state word oriented random access memory responsive to said computer system, said memory having k binary word storage positions, each of said word storage positions having a binary bit positions for storing test data, and x binary bit positions for storing control data, where k is an integer having a magnitude of at least four hundred and x is an integer having a magnitude of at least four; controllable shift register means coupled to said memory and adapted to store n binary bits, said shift register means being adapted to successively receive n binary bits of test data from said memory; n pin circuits means coupled to said controllable shift register means and said n contact pins of a device under test; control means for controlling said shift register means and each of said n pin circuit means, said control means interconnecting said shift register means and said n pin circuit means, said control means cooperating with said computer system and being successively responsive to binary values obtained from said x binary bit positions of successive ones of said k binary word positions of said memory, whereby a multiple of k n binary bit words of Serial/Parallel test data may be stored in said k binary word storage positions of said word oriented random access memory.

Claim 25

An electronic tester for testing an electronic device having n terminals, said n terminals including, y input terminals for accepting electrical manifestations as inputs, z output terminals for electrically manifesting outputs, and p parameter terminals for accepting electrical energy source manifestations, where the sum of y, z and p is equal to n, and n is an integer having any value in the range of one hundred to five hundred, said tester being operative under control of a test program having at least m test steps and at least one test pattern, each said test pattern including m discrete words, each of said m test steps utilizing a distinct one of said m discrete words, each of said m discrete words containing n binary bits, where m is an integer having any value in the range one hundred to one thousand, said test including: a system controller having storage means for storing m-k of said m words and k word portions, where k is any integer in the range of zero through m-l; electronic means coupling said storage means to said n terminals of said device under test; additional means under control of said system controller and cooperating with said storage means and said electronic means to impress during each test pattern step, then n binary bits of a discrete one of said m words on said n terminals of said device under test; said electronic means including word construction means responsive to said additional means for providing to said electronic means during each of said m steps a discrete n binary bit word containing n discrete electrical manifestations of a binary one or zero, said word construction means in cooperation with said additional means utilizing said n binary bits of at least one of said m-k of said m words to construct said k word portions into k discrete words having n binary bits, whereby a discrete binary word having n discrete electrical manifestations representing binarY ones and/or zeros is impressed on said n terminals of said device under test during each of said m test steps.

Claim 26

An electronic tester for testing an electronic device having n terminals, said n terminals including, y input terminals for accepting electrical manifestations as inputs, z output terminals for electrically manifesting outputs, and p parameter terminals for accepting electrical energy source manifestations, where the sum of y, z and p is equal to n, and n is an integer having any value in the range of one hundred to five hundred, said tester being operative under control of a test program having at least m test steps and at least one test pattern, each said test pattern including m discrete words, each of said m test steps utilizing a distinct one of said m discrete words, each of said m discrete words containing n binary bits, where m is an integer having any value in the range one hundred to one thousand, said test including: a system controller having storage means for storing m-k of said m words and k word portions, where k is any integer in the range of zero through m-l; electronic means coupling said storage means to said n terminals of said device under test; additional means under control of said system controller and cooperating with said storage means and said electronic means to impress during each test pattern step, then n binary bits of a discrete one of said m words on said n terminals of said device under test; said electronic means including word construction means responsive to said additional means for providing to said electronic means during each of said m steps a discrete n binary bit word containing n discrete electrical manifestations of a binary one or zero, said word construction means in cooperation with said additional means utilizing said n binary bits of at least one of said m-k of said m words to construct said k word portions into k discrete words having n binary bits, whereby a discrete binary word having n discrete electrical manifestations representing binarY ones and/or zeros is impressed on said n terminals of said device under test during each of said m test steps.

Claim 27

An electronic tester operative under control of a computer system for testing large scale integration devices, said tester including: word oriented random access storage means coupled to said computer system; shiftable data storage means coupled to said word oriented random access storage means; settable circuit means intercoupling said shiftable data storage means and a large scale integration device under test; and control means responsively coupled to said computer system, said control means coupled to said shiftable data storage means and said settable circuit means for controlling the operation of said tester, whereby said tester will subject said device under test to a test pattern having a greater number of test data words than said random access word oriented storage means has capacity to store.

Claim 28

An electronic tester operative under control of a computer system for testing large scale integration devices, said tester including: word oriented random access storage means coupled to said computer system; shiftable data storage means coupled to said word oriented random access storage means; settable circuit means intercoupling said shiftable data storage means and a large scale integration device under test; and control means responsively coupled to said computer system, said control means coupled to said shiftable data storage means and said settable circuit means for controlling the operation of said tester, whereby said tester will subject said device under test to a test pattern having a greater number of test data words than said random access word oriented storage means has capacity to store.

Claim 29

An electronic test system for testing devices fabricated by large scale integration techniques, said devices having n contact pads, each of said n contact pads having a function associated therewith such as one of the following, data input, data output, energy source input, gate output, gate input, clock output, clock input, etc., where n is an integer equal to at least fifty, said electronic test system employing at least one test pattern under control of a system test program, said test pattern including at least m test steps and each of said m test steps utilizing a discrete test word having n discrete electrical manifestations of logical ones and/or zeros, where m is an integer having any value in the range of one hundred to one thousand, said test system including: a system controller operative under control of said test program for overall monitoring and controlling of each test step of said test pattern, said system controller including bulk storage means for storing test data; a solid state word oriented random access memory coupled to said system controller and having a capacity capable of storing z binary words in z binary word positions of storage, each of said z word positions of storage of said random access memory including one through n binary bit positions for storing n binary bits of test data and at least four binary bit positions for storing operational code specifying bits for manifesting the operation to be executed by said test system for the associated n binary bits of test data, where z is an integer; n settable pin circuits each having a data input and an output, each of said n pin circuits including settable means for setting the function of said pin circuit; connection means connecting each of said n outputs of said n pin circuits to a discrete one of said n contact pads of said device under test; high speed recirculating shift register means having one through n stages, each stage having an input and an output, each stage intercoupling discrete first and second ones of said n stages, each stage being adapted and controllable to store a binary bit of data and to shift said binary bit of data to either said discrete first one, or said discrete second one coupled to said stage; auxiliary means coupled to said high speed recirculating shift register means for receiving and storing an indication of the number of stages binary data stored in said shift register means is to be shifted, said auxilliary means also being adapted to provide a manifestation when the binary data stored in said shift register means has been shifted the number of stages called by said indication: connection means connecting said n inputs of said n stages of said shift register means and said word oriented random access memory and connecting said n outputs of said n stages of said shift register means and said n inputs of said n pin circuit means; decode circuit means intercoupling said system controller, said word oriented random acCess memory, said shift register means, auxiliary means and said n pin circuit means, specifying bits from said word oriented random access memory and to cause said test system to execute the operation specified by said operational code specifying bits.

Claim 30

An electronic test system for testing devices fabricated by large scale integration techniques, said devices having n contact pads, each of said n contact pads having a function associated therewith such as one of the following, data input, data output, energy source input, gate output, gate input, clock output, clock input, etc., where n is an integer equal to at least fifty, said electronic test system employing at least one test pattern under control of a system test program, said test pattern including at least m test steps and each of said m test steps utilizing a discrete test word having n discrete electrical manifestations of logical ones and/or zeros, where m is an integer having any value in the range of one hundred to one thousand, said test system including: a system controller operative under control of said test program for overall monitoring and controlling of each test step of said test pattern, said system controller including bulk storage means for storing test data; a solid state word oriented random access memory coupled to said system controller and having a capacity capable of storing z binary words in z binary word positions of storage, each of said z word positions of storage of said random access memory including one through n binary bit positions for storing n binary bits of test data and at least four binary bit positions for storing operational code specifying bits for manifesting the operation to be executed by said test system for the associated n binary bits of test data, where z is an integer; n settable pin circuits each having a data input and an output, each of said n pin circuits including settable means for setting the function of said pin circuit; connection means connecting each of said n outputs of said n pin circuits to a discrete one of said n contact pads of said device under test; high speed recirculating shift register means having one through n stages, each stage having an input and an output, each stage intercoupling discrete first and second ones of said n stages, each stage being adapted and controllable to store a binary bit of data and to shift said binary bit of data to either said discrete first one, or said discrete second one coupled to said stage; auxiliary means coupled to said high speed recirculating shift register means for receiving and storing an indication of the number of stages binary data stored in said shift register means is to be shifted, said auxilliary means also being adapted to provide a manifestation when the binary data stored in said shift register means has been shifted the number of stages called by said indication: connection means connecting said n inputs of said n stages of said shift register means and said word oriented random access memory and connecting said n outputs of said n stages of said shift register means and said n inputs of said n pin circuit means; decode circuit means intercoupling said system controller, said word oriented random acCess memory, said shift register means, auxiliary means and said n pin circuit means, specifying bits from said word oriented random access memory and to cause said test system to execute the operation specified by said operational code specifying bits.

Claim 31

An electronic test system as recited in claim 23 wherein said high speed recirculating shift register means is a closed loop binary shift register having n stages, said shift register being adapted to receive in parallel an input word having n binary bits and provide in parallel an output word having n binary bits, where said output word is said input word shifted zero, one, or more, shift register stages, said shift register including: n binary stages; each of said n binary stages having, a data stage input terminal, a data stage control terminal, a data interstage input terminal, a data interstage control terminal, an interstage output terminal, a stage output terminal, a register accept data control terminal, and a shift data control terminal; a first AND circuit having a first input connected to said data stage input terminal, a second input connected to said data stage control terminal, and an output; a second AND circuit having a first input connected to said data interstage control terminal, a second input connected to said data interstage input terminal, and an output; an OR circuit having a first input connected to said output of said first AND circuit, a second input connected to said output of said second AND circuit, and an output; a first settable latch circuit having a first-input connected to said output of said OR circuit, a second input connected to said register accept data control terminal, and an output connected to said stage output terminal; a second settable latch circuit having a first input connected to said output of said first settable latch circuit, a second input connected to said shift data control terminal and an output connected to said data interstage output terminal; n connections respectively connecting said interstage output terminals of said 1st, 2nd, 3rd, 4th, 5thn-3, n-2, 1-1 and nth stages to said data interstage input terminals of said nth 1,2,3,4 n-4, n-3, n-2 and n- 1th stages; first connection means connecting in common the data stage control terminals of said n stages; second connection means connecting in common the data interstage control terminals of said n stages; third connection means connecting in common the register accept data control terminal of said n stages; and, fourth connection means connecting in common the shift data control terminals of said n stages, whereby an n bit binary word impressed on said n data stage input terminals will be accepted by, and stored in said n first settable latches when said first connection means and said third connection means are respectively conditioned by electrical manifestations impressed thereon, and subsequent thereto the n binary bit word stored in said n first settable latches will be shifted one stage from each successive time said second and fourth connection means are respectively conditioned by electrical manifestations impressed thereon.

Claim 32

In an electronic test system as recited in claim 23 wherein a first discrete n binary bit word of parallel test data and a second discrete n binary bit word containing serial test data are logically rearranged and reconstructed to provide any number of discrete n binary bit test data words up to a maximum of n+1 discrete n binary bit test data words.

Claim 33

In an electronic test system as recited in claim 23 wherein said test pattern includes mixed serial/parallel test data.

Claim 34

In an electronic test system as recited in claim 23 where z is an integer less than m, and said m discrete n binary bit test wOrds are constructed from z n binary bit words stored in said solid state word oriented random access memory.

Claim 35

In an electronic test system as recited in claim 27 where said m discrete n binary bit test words consist of mixed serial/parallel test data.

Claim 36

In an electronic test system as recited in claim 23, wherein m is greater than z in magnitude, and where a test pattern having m test steps each employing an n binary bit test word is virtually stored in said z binary word storage positions of said solid state word oriented random access memory.

Claim 37

An electronic test system as recited in claim 23 further characterized by at least one of said n settable pin circuits being a pin circuit for use in a high speed tester for testing large scale integration devices, where said tester employs at least a plurality of operational code specifying bits, a SET DISCONNECT electrical manifestation, a TEST PARALLEL electrical manifestation, a SET PIN SERIAL electrical manifestation, a TEST TESTER electrical manifestation, a SET-UP mode electrical instruction, a SET CLOCK 1 electrical manifestation, a TEST SERIAL electrical manifestation, a TEST mode electrical instruction, DRIVE TIME pulses, STROBE TIME pulses and CLOCK 1 pulses and provides at least GO/NO-GO pulses, said pin circuits being conditionable to perform a plurality of functions expressly including the following, driver, load, open and ground, said pin circuit comprising: a test data input terminal for accepting test data and a DUT connection terminal for connection to a contact pin, or pad, of a large Scale integration device under test; first, second, third, fourth, fifth, sixth, seventh and eighth settable polarity hold latches, each of said latches having an information input, a control input and an output; first, second and third switches, each of said switches having first and second terminal means and a control input whereby the open or closed status of said switch may be controlled by an electrical condition; first, second and third AND circuits respectively having first and second inputs and an output; fourth, fifth, sixth and seventh AND circuits respectively having first, second and third inputs and an output; first and second EXCLUSIVE OR circuits respectively having first and second inputs and an output; first and second OR circuits respectively having first and second inputs and an output; a settable DRIVER circuit having an input and output, said DRIVER circuit being adapted to provide a first electrical manifestation at said output thereof in response to a first electrical condition impressed on said input thereof and a second electrical manifestation at said output thereof in response to a second electrical condition impressed on said input thereof; a settable DETECTOR circuit having an input and an output, said DETECTOR circuit being adapted to provide as an output a first signal when an electrical status equal or to or less than a predetermined set standard is impressed on the input thereof and a second signal when an electrical status greater than said predetermined set standard is impressed on the input thereof; an electrical load; first connection means connecting in common said data input terminal of said pin circuit, said information input of said first latch, said information input of said second latch, said second input of said first AND circuit, said information input of said sixth latch, said information input of said eighth latch and said second input of said first EXCLUSIVE OR circuit; said control input of said first latch being adapted to receive a SET Disconnect electrical command, a first INVERTER circuit connected between said output of said first latch and said control input of said first switch; second connection means connecting in common said first terminal means of said first, second and third switches and said input of said DETECTOR circuit; third connection means connecting saId output of said DRIVER circuit to said second terminal means of said third switch; fourth connection means connecting said second terminal means of said first switch and said DUT connection terminal of said PIN circuit; fifth connection means connecting said second terminal means of said second switch to said electrical load; said first input of said first OR circuit being adapted to receive a TEST PARALLEL electrical command, said control input of said second latch being adapted to receive a SET PIN SERIAL electrical command, said second input of said first OR circuit being connected to said output of said second latch, said output of said first OR circuit being connected to said first input of said fourth AND circuit and said first input of said second AND circuit; said information input of said third latch being adapted to receive an electrical manifestation of a first one of said plurality of Operational Code specifying bits, said output of said third latch being connected to said control input of said second switch; said first input of said second OR circuit being adapted to receive a TEST TESTER electrical command, said output of said second OR circuit being connected to said first input of said sixth AND circuit; said information input of said fourth latch being adapted to receive an electrical manifestation of a second one of said plurality of operational code specifying bits, said output of said fourth latch being connected to the control input of said third switch and the second input of said second AND circuit, a second INVERTER circuit connected between the output of said fourth latch and said second input of said fourth AND circuit; said information input of said fifth latch being adapted to receive an electrical manifestation of a third one of said plurality of operational code specifying bits; a third INVERTER circuit connected between the output of said fifth latch and the third input of said fourth AND circuit; said first input of said first AND circuit being adapted to receive a SET-UP mode electrical instruction, said output of said first AND circuit being connected to the control inputs of said third, fourth and fifth latches; said first input of said fifth AND circuit being connected to said output of said second AND circuit, said second input of said fifth AND circuit being adapted to receive Drive Time pulses, said third input of said fifth AND circuit, said third input of said sixth AND circuit and said first input of said third AND circuit being respectively adapted to receive a TEST mode electrical instruction, said output of said fifth AND circuit being connected to said control input of said sixth latch, said output of said sixth latch being connected to said second input of said second Exclusive OR circuit, and said output of siad second Exclusive OR circuit being connected to said input of said Driver circuit; said first input of said first Exclusive OR circuit being connected to the output of said DETECTOR circuit, the output of said first Exclusive OR circuit being connected to the information input of said seventh latch; said second input of said third AND circuit being adapted to receive STROBE-Time pulses, the output of said third AND circuit being connected to said control input of said seventh latch, the output of said seventh latch being connected to said second input of said sixth AND circuit, and the output of said sixth AND circuit being adapted to provide a GO/NO-GO electrical representation; said control input of said eighth latch being adapted to receive a SET CLOCK ONE command, said output of said eighth latch being connected to said first input of said seventh AND circuit, said second input of said seventh AND circuit being adapted to receive a TEST SERIAL command, said third input of said seventh AND circuit being adapted to receive CLOCK 1 pulses, and said output of said seventh AND circuit being connected to saiD first input of said second Exclusive OR circuit; whereby said pin circuit is conditionable to perform any one of said plurality of functions respectively in accord with the operation of said tester as called for by said commands and said plurality of operational code specifying bits.

Claim 38

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specified the operation SET Disconnect and in response thereto said test system executes the operation SET Disconnect.

Claim 39

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET NUMBER of SERIAL TESTS, and in response thereto said test system executes the operation SET NUMBER of SERIAL TESTS.

Claim 40

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET PIN SERIAL and in response thereto said test system executes the operation SET PIN SERIAL.

Claim 41

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET CLOCK 1 and in response thereto said test system executes the operation SET CLOCK 1.

Claim 42

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation TEST TESTER and in response thereto said test system executes the operation TEST TESTER.

Claim 43

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation TEST SERIAL and in response thereto said test system executes the operation TEST SERIAL.

Claim 44

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation TEST PARALLEL and in response thereto said test system executes the operation TEST PARALLEL.

Claim 45

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, OUT, MASK and in response thereto said test system executes the operation SET-LOAD, OUT, MASK.

Claim 46

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, OUT, MASK and in response thereto said test system executes the operation SET-LOAD, OUT, MASK.

Claim 47

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, IN, MASK and in response thereto said test system executes the operation SET-LOAD, IN, MASK.

Claim 48

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, IN, MASK and in response thereto said test system executes the operation SET-LOAD, IN, MASK.

Claim 49

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, OUT, MASK and in response thereto said test system executes the operation SET-LOAD, OUT, MASK.

Claim 50

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, OUT, MASK and in response thereto said test system executes the operation SET-LOAD, OUT, MASK.

Claim 51

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, IN, MASK and in response thereto said test system executes tHe operation SET-LOAD, IN MASK.

Claim 52

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least one of said m test steps specifies the operation SET-LOAD, IN, MASK and in response thereto said test system executes the operation SET-LOAD, IN, MASK.

Claim 53

An electronic test system as recited in claim 23 wherein said operational code specifying bits during at least two consecutive ones of said m test steps respectively specify TEST PARALLEL and TEST SERIAL and in response thereto said test system consecutively executes the operations TEST PARALLEL and TEST SERIAL.

Claim 54

An electronic test system as recited in claim 23 wherein said Decode circuit means is a Decode circuit for use in a high speed electronic test system for testing high density circuit devices where said tester performs a number of operations respectively initiated by said operational code specifying bits, said Decode circuit being adapted to receive and respond to four operational codes specifying bits, Y-Time pulses and a STOP SERIAL TEST command in the form of an electrical manifestation, said Decode circuit being adapted to provide a plurality of commands respectively in the form of electrical manifestations, said plurality of electrical manifestations including the following SET NUMBER SERIAL TESTS command, TEST SERIAL command, NOT TEST SERIAL command, TEST MODE command, SET DISCONNECT command, SET PIN SERIAL command, TEST PARALLEL command, TEST TESTER command, a SETUP MODE command, a SET CLOCK 1 command, a STOP RAM command, Y1-Time pulses, Z pulses and Z pulses, said Decode circuit being operative during each test cycle of a test operation including a sizeable number of test cycles, where each test cycle of said test system is controlled, at least in part, by one or more of said electrical commands, said Decode circuit comprising: first, second, third and fourth input terminals for respectively receiving said first, second, third and fourth operational code specifying bits, and a fifth input terminal for receiving said Y-Time pulses; first, second, ninth and twelfth AND circuits respectively having first and second inputs and an output; sixth, seventh, eighth and tenth AND circuits respectively having first, second and third inputs and an output; third, fourth, fifth and eleventh AND circuits respectively having first, second, third and fourth inputs and an output; first and second monostable devices respectively having an input and an output; a bistable device having a SET input, a RESET input and an output; an OR circuit having first and second inputs and an output; said first input of said first AND circuit being connected to said first input terminal of said Decode circuit, a first INVERTER circuit connected between said second input terminal of said Decode circuit and said second input of said first AND circuit, and said output of said first AND circut being connected to said first input of said third AND circuit, said fourth input of said fourth AND circuit, said first input of said fifth AND circuit, and said second input of said eleventh AND circuit; said first input of said second AND circuit being connected to said first input terminal of said Decode circuit, said second input of said AND circuit being connected to said second input terminal of said Decode circuit, said output of said second AND circuit being connected to said first input of said sixth AND circuit, said first input of said seventh AND circuit, said first input of said eighth AND circuit, and said third input of said tenth AND circuit, and being adapted to provide said TEST MODE command; a second INVERTER circuit connected between said first input terminal of said Decode circuit and said second input of said ninth AND circuit; a third INVERTER circuit connected between said third input terminal of said Decode circuit and said third input of said fiRst AND circuit, said third input of said fifth AND circuit, and said third input of said eighth AND circuit; a fourth INVERTER circuit connected between said fourth input terminal of said Decode circuit and said fourth input of said first AND circuit, said third input of said second AND circuit, and said third input of said seventh AND circuit; said second input of said third AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said third AND circuit being adapted to provide said SET NUMBER OF SERIAL TESTS command; said first input of said fourth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said fourth AND circuit being connected to said third input terminal of said Decode circuit, and said output of said fourth AND circuit being adapted to provide said SET DISCONNECT command; said second input of said fifth AND circuit being connected to said fifth input terminal of said Decode circuit, said fourth input of said fifth AND circuit being connected to said fourth input terminal of said Decode circuit, and said output of said fifth AND circuit being adapted to provide a SET PIN SERIAL command; said second input of said sixth AND circuit being connected to said third input terminal of said Decode circuit, said third input of said sixth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said sixth AND circuit being adapted to provide said TEST PARALLEL command; said second input of said seventh AND circuit being connected to said third input terminal of said Decode circuit, said output of said seventh AND circuit being connected to said second input of said twelfth AND circuit and said input of said second monostable device, and said output of said seventh AND circuit being adapted to provide said TEST SERIAL command; a fifth INVERTER circuit connected to said output of said seventh AND circuit and said second input of said OR circuit; said set input of said bistable device being connected to said output of said second monstable device, said output of said second monostable device being adapted to provide said Z pulses, said reset input of said bistable device being connected to said output of said first monostable device; said first input of said tenth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said tenth AND circuit being connected to said output of said bistable device, said output of said bistable device being adapted to provide said STOP RAM command, and said output of said tenth AND circuit being adapted to provide said Y1 Time pulses; said input of said first monstable device being adapted to receive said STOP SERIAL TEST command; said second input of said eighth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said eighth AND circuit being adapted to provide said TEST TESTER command, said first input of said ninth AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said ninth AND circuit being adapted to provide said SET-UP MODE command; said first, third and fourth inputs of said eleventh AND circuit being respectively connected to said fifth, third and fourth input terminals of said Decode circuit, said output of said eleventh AND circuit being adapted to provide said SET CLOCK 1 command; a sixth INVERTER circuit having an input and an output and coupling said output of said first monostable device to said second input of said twelfth AND circuit, said output of said sixth INVERTER circuit being adapted to provide said Z pulses and said output of said twelfth AND circuit being adapted to provide a time delayed TEST SERIAL command; and said first input of said OR circuit being connected to said output of said first monostable device, said output oF said OR circuit being adapted to provide a time-delayed NOT TEST SERIAL command; whereby a test system employing said Decode circuit will execute upon command a SET SERIAL NUMBER of TESTS operation, a TEST SERIAL operation, a SET DISCONNECT operation, a SET PIN SERIAL operation, a TEST PARALLEL operation, or a TEST TESTER operation.

Claim 55

A closed loop binary shift register having n stages, said shift register being adapted to receive in parallel an input word having n binary bits and provide in parallel an output word having n binary bits, where said output word is said input word shifted zero, one, or more, shift register stages, said shift register including: n binary stages; each of said n binary stages having, a data stage input terminal, a data stage control terminal, a data interstage input terminal, a data interstage control terminal, an interstage output terminal, a stage output terminal, a register accept data control terminal, and a shift data control terminal; a first AND circuit having a first input connected to said data stage input terminal, a second input connected to said data stage control terminal, and an output; a second AND circuit having a first input connected to said data interstage control terminal, a second input connected to said data interstage input terminal, and an output; an OR circuit having a first input connected to said output of said first AND circuit, a second input connected to said output of said second AND circuit, and an output; a first settable latch circuit having a first input connected to said output of said OR circuit, a second input connected to said register accept data control terminal, and an output connected to said stage output terminal; a second settable latch circuit having a first input connected to said output of said first settable latch circuit, a second input connected to said shift data control terminal and an output connected to said data interstage output terminal; n connections respectively connecting said interstage output terminals of said 1st, 2nd, 3rd, 4th, 5th----n-3, n-2, n-1 and nth stages to said data interstage input terminals of said nth 1, 2, 3, 4----n-4, n-3, n-2 and n-1th stages; first connection means connecting in common the data stage control terminals of said n stages; second connection means connecting in common the data interstage control terminals of said n stages; third connection means connecting in common the register accept data control terminal of said n stages; and, fourth connection means connecting in common the shift data control terminals of said n stages, whereby an n bit binary word impressed on said n data stage input terminals will be accepted by, and stored in said n first settable latches when said first connection means and said third connection means are respectively conditioned by electrical manifestations impressed thereon, and subsequent thereto the n binary bit word stored in said n first settable latches will be shifted one stage for each successive time said second and fourth connection means are respectively conditioned by electrical manifestations impressed thereon.

Claim 56

A closed loop binary shift register having n stages, said shift register being adapted to receive in parallel an input word having n binary bits and provide in parallel an output word having n binary bits, where said output word is said input word shifted zero, one, or more, shift register stages, said shift register including: n binary stages; each of said n binary stages having, a data stage input terminal, a data stage control terminal, a data interstage input terminal, a data interstage control terminal, an interstage output terminal, a stage output terminal, a register accept data control terminal, and a shift data control terminal; a first AND circuit having a first input connected to said data stage input terminal, a second input connected to said data stage control terminal, and an output; a second AND circuit having a first input connected to said data interstage control terminal, a second input connected to said data interstage input terminal, and an output; an OR circuit having a first input connected to said output of said first AND circuit, a second input connected to said output of said second AND circuit, and an output; a first settable latch circuit having a first input connected to said output of said OR circuit, a second input connected to said register accept data control terminal, and an output connected to said stage output terminal; a second settable latch circuit having a first input connected to said output of said first settable latch circuit, a second input connected to said shift data control terminal and an output connected to said data interstage output terminal; n connections respectively connecting said interstage output terminals of said 1st, 2nd, 3rd, 4th, 5th----n-3, n-2, n-1 and nth stages to said data interstage input terminals of said nth 1, 2, 3, 4----n-4, n-3, n-2 and n-1th stages; first connection means connecting in common the data stage control terminals of said n stages; second connection means connecting in common the data interstage control terminals of said n stages; third connection means connecting in common the register accept data control terminal of said n stages; and, fourth connection means connecting in common the shift data control terminals of said n stages, whereby an n bit binary word impressed on said n data stage input terminals will be accepted by, and stored in said n first settable latches when said first connection means and said third connection means are respectively conditioned by electrical manifestations impressed thereon, and subsequent thereto the n binary bit word stored in said n first settable latches will be shifted one stage for each successive time said second and fourth connection means are respectively conditioned by electrical manifestations impressed thereon.

Claim 57

A pin circuit for use in a high speed tester for testing large scale integration devices, where said tester employs at least a plurality of operational code specifying bits, a SET DISCONNECT electrical manifestation, a TEST PARALLEL electrical manifestation, a SET PIN SERIAL electrical manifestation, a TEST TESTER electrical manifestation, a SET-UP mode electrical instruction, a SET CLOCK 1 electrical manifestation, a TEST SERIAL electrical manifestation, a TEST mode electrical instruction, DRIVE TIME pulses, STROBE TIME pulses and CLOCK 1 pulses and provides at least GO/NO-GO pulses, said pin circuit being conditionable to Perform a plurality of functions expressly including the following, driver, load, open and ground, said pin circuit comprising: a test data input terminal for accepting test data and a DUT connection terminal for connection to a contact pin, or pad, of a large scale integration device under test; first, second, third, fourth, fifth, sixth, seventh and eighth settable polarity hold latches, each of said latches having an information input, a control input and an output; first, second and third switches, each of said switches having first and second terminal means and a control input whereby the open or closed status of said switch may be controlled by an electrical condition; first, second and third AND circuits respectively having first and second inputs and an output; fourth, fifth, sixth and seventh AND circuits respectively having first, second and third inputs and an output; first and second EXCLUSIVE OR circuits respectively having first and second inputs and an output; first and second OR circuits respectively having first and second inputs and an output; a settable DRIVER circuit having an input and output, said DRIVER circuit being adapted to provide a first electrical manifestation at said output thereof in response to a first electrical condition impressed on said input thereof and a second electrical manifestation at said output thereof in response to a second electrical condition impressed on said input thereof; a settable DETECTOR circuit having an input and an output, said DETECTOR circuit being adapted to provide as an output a first signal when an electrical status equal to or less than a predetermined set standard is impressed on the input thereof and a second signal when an electrical status greater than said predetermined set standard is impressed on the input thereof; an electrical load,; first connection means connecting in common said data input terminal of said pin circuit, said information input of said first latch, said information input of said second latch, said second input of said first AND circuit, said information input of said sixth latch, said information input of said eighth latch, and said second input of said first EXCLUSIVE OR circuit; said control input of said first latch being adapted to receive a SET Disconnect electrical command, a first INVERTER circuit connected between said output of said first latch and said control input of said first switch; second connection means connecting in common said first terminal means of said first, second and third switches and said input of said DETECTOR circuit; third connection means connecting said output of said Driver circuit to said second terminal means of said third switch; fourth connection means connecting said second terminal means of said first switch and said DUT connection terminal of said PIN circuit; fifth connection means connecting said second terminal means of said second switch to said electrical load; said first input of said first OR circuit being adapted to receive a TEST PARALLEL electrical command, said control input of said second latch being adapted to receive a SET PIN SERIAL electrical command, said second input of said first OR circuit being connected to said output of said second latch, said output of said first OR circuit being connected to said first input of said fourth AND circuit and said first input of said second AND circuit; said information input of said third latch being adapted to receive an electrical manifestation of a first one of said plurality of Operational Code specifying bits, said output of said third latch being connected to said control input of said second switch; said first input of said second OR circuit being adapted to receive a TEST TESTER electrical command, said output of said second OR circuit being connected to said first input of said sixth AND circuit; said information input of said fourth latch being adapted to receive an electrical manifestation of a second one of said plurality Of operational code specifying bits, said output of said fourth latch being connected to the control input of said third switch and the second input of said second AND circuit, a second INVERTER circuit connected between the output of said fourth latch and said second input of said fourth AND circuit; said information input of said fifth latch being adapted to receive an electrical manifestation of a third one of said plurality of operational code specifying bits; a third INVERTER circuit connected between the output of said fifth latch and the third input of said fourth AND circuit; said first input of said first AND circuit being adapted to receive a SET-UP mode electrical instruction, said output of said first AND circuit being connected to the control inputs of said third, fourth and fifth latches; said first input of said fifth AND circuit being connected to said output of said second AND circuit; said second input of said fifth AND circuit being adapted to receive Drive Time pulses, said third input of said fifth AND circuit, said third input of said sixth AND circuit and said first input of said third AND circuit being respectively adapted to receive a TEST mode electrical instruction, said output of said fifth AND circuit being connected to said control input of said sixth latch, said output of said sixth latch being connected to said second input of said second Exclusive OR circuit and said output of said second Exclusive OR circuit being connected to said input of said Driver circuit; said first input of said first Exclusive OR circuit being connected to the output of said DETECTOR circuit, the output of said first Exclusive OR circuit being connected to the information input of said seventh latch; said second input of said third AND circuit being adapted to receive STROBE-TIME pulses, the output of said third AND circuit being connected to said control input of said seventh latch, the output of said seventh latch being connected to said second input of said sixth AND circuit, and the output of said sixth AND circuit being adapted to provide a GO/NO-GO electrical representation; said control input of said eighth latch being adapted to receive a SET CLOCK 1 command, said output of said eighth latch being connected to said first input of said seventh AND circuit, said second input of said seventh AND circuit being adapted to receive a TEST SERIAL command, said third input of said seventh AND circuit being adapted to receive CLOCK 1 pulses, and said output of said seventh AND circuit being connected to said first input of said second Exclusive OR circuit; whereby said pin circuit is conditionable to perform any one of said plurality of functions respectively in accord with the operation of said tester as called for by said commands and said plurality of operational code specifying bits.

Claim 58

A pin circuit for use in a high speed tester for testing large scale integration devices, where said tester employs at least a plurality of operational code specifying bits, a SET DISCONNECT electrical manifestation, a TEST PARALLEL electrical manifestation, a SET PIN SERIAL electrical manifestation, a TEST TESTER electrical manifestation, a SET-UP mode electrical instruction, a SET CLOCK 1 electrical manifestation, a TEST SERIAL electrical manifestation, a TEST mode electrical instruction, DRIVE TIME pulses, STROBE TIME pulses and CLOCK 1 pulses and provides at least GO/NO-GO pulses, said pin circuit being conditionable to Perform a plurality of functions expressly including the following, driver, load, open and ground, said pin circuit comprising: a test data input terminal for accepting test data and a DUT connection terminal for connection to a contact pin, or pad, of a large scale integration device under test; first, second, third, fourth, fifth, sixth, seventh and eighth settable polarity hold latches, each of said latches having an information input, a control input and an output; first, second and third switches, each of said switches having first and second terminal means and a control input whereby the open or closed status of said switch may be controlled by an electrical condition; first, second and third AND circuits respectively having first and second inputs and an output; fourth, fifth, sixth and seventh AND circuits respectively having first, second and third inputs and an output; first and second EXCLUSIVE OR circuits respectively having first and second inputs and an output; first and second OR circuits respectively having first and second inputs and an output; a settable DRIVER circuit having an input and output, said DRIVER circuit being adapted to provide a first electrical manifestation at said output thereof in response to a first electrical condition impressed on said input thereof and a second electrical manifestation at said output thereof in response to a second electrical condition impressed on said input thereof; a settable DETECTOR circuit having an input and an output, said DETECTOR circuit being adapted to provide as an output a first signal when an electrical status equal to or less than a predetermined set standard is impressed on the input thereof and a second signal when an electrical status greater than said predetermined set standard is impressed on the input thereof; an electrical load,; first connection means connecting in common said data input terminal of said pin circuit, said information input of said first latch, said information input of said second latch, said second input of said first AND circuit, said information input of said sixth latch, said information input of said eighth latch, and said second input of said first EXCLUSIVE OR circuit; said control input of said first latch being adapted to receive a SET Disconnect electrical command, a first INVERTER circuit connected between said output of said first latch and said control input of said first switch; second connection means connecting in common said first terminal means of said first, second and third switches and said input of said DETECTOR circuit; third connection means connecting said output of said Driver circuit to said second terminal means of said third switch; fourth connection means connecting said second terminal means of said first switch and said DUT connection terminal of said PIN circuit; fifth connection means connecting said second terminal means of said second switch to said electrical load; said first input of said first OR circuit being adapted to receive a TEST PARALLEL electrical command, said control input of said second latch being adapted to receive a SET PIN SERIAL electrical command, said second input of said first OR circuit being connected to said output of said second latch, said output of said first OR circuit being connected to said first input of said fourth AND circuit and said first input of said second AND circuit; said information input of said third latch being adapted to receive an electrical manifestation of a first one of said plurality of Operational Code specifying bits, said output of said third latch being connected to said control input of said second switch; said first input of said second OR circuit being adapted to receive a TEST TESTER electrical command, said output of said second OR circuit being connected to said first input of said sixth AND circuit; said information input of said fourth latch being adapted to receive an electrical manifestation of a second one of said plurality Of operational code specifying bits, said output of said fourth latch being connected to the control input of said third switch and the second input of said second AND circuit, a second INVERTER circuit connected between the output of said fourth latch and said second input of said fourth AND circuit; said information input of said fifth latch being adapted to receive an electrical manifestation of a third one of said plurality of operational code specifying bits; a third INVERTER circuit connected between the output of said fifth latch and the third input of said fourth AND circuit; said first input of said first AND circuit being adapted to receive a SET-UP mode electrical instruction, said output of said first AND circuit being connected to the control inputs of said third, fourth and fifth latches; said first input of said fifth AND circuit being connected to said output of said second AND circuit; said second input of said fifth AND circuit being adapted to receive Drive Time pulses, said third input of said fifth AND circuit, said third input of said sixth AND circuit and said first input of said third AND circuit being respectively adapted to receive a TEST mode electrical instruction, said output of said fifth AND circuit being connected to said control input of said sixth latch, said output of said sixth latch being connected to said second input of said second Exclusive OR circuit and said output of said second Exclusive OR circuit being connected to said input of said Driver circuit; said first input of said first Exclusive OR circuit being connected to the output of said DETECTOR circuit, the output of said first Exclusive OR circuit being connected to the information input of said seventh latch; said second input of said third AND circuit being adapted to receive STROBE-TIME pulses, the output of said third AND circuit being connected to said control input of said seventh latch, the output of said seventh latch being connected to said second input of said sixth AND circuit, and the output of said sixth AND circuit being adapted to provide a GO/NO-GO electrical representation; said control input of said eighth latch being adapted to receive a SET CLOCK 1 command, said output of said eighth latch being connected to said first input of said seventh AND circuit, said second input of said seventh AND circuit being adapted to receive a TEST SERIAL command, said third input of said seventh AND circuit being adapted to receive CLOCK 1 pulses, and said output of said seventh AND circuit being connected to said first input of said second Exclusive OR circuit; whereby said pin circuit is conditionable to perform any one of said plurality of functions respectively in accord with the operation of said tester as called for by said commands and said plurality of operational code specifying bits.

Claim 59

A Decode circuit for use in a high speed electronic test system for testing high density circuit devices said tester performing a number of operations respectively initiated by operational code specifying bits, said Decode circuit being adapted to receive and respond to four operational codes specifying bits, Y-Time pulses and a STOP SERIAL TEST command in the form of an electrical manifestation, said Decode circuit being adapted to provide a plurality of commands respectively in the form of electrical manifestations, said plurality of electrical manifestations including the following SET NUMBER SERIAL TESTS command, TEST SERIAL command, NOT TEST SERIAL command, TEST MODE command, SET DISCONNECT command, SET PIN SERIAL command, TEST PARALLEL command, TEST TESTER command, a SET-UP MODE command, a SET CLOCK 1 command, a STOP RAM command, Y1-TIME pulses, Z pulses and z pulses, said Decode circuit being operative during each test cycle of a test operations including a sizeable number of test cycles, where each test cycle of said test system is controlleD, at least in part, by one or more of said electrical commands, said Decode circuit comprising; first, second, third and fourth input terminals for respectively receiving said first, second, third and fourth operational code specifying bits, and a fifth input terminal for receiving said Y-TIME pulses; first, second, ninth, ninth and twelfth AND circuits respectively having first and second inputs and an output; sixth, seventh, eighth and tenth AND circuits respectively having first, second and third inputs and an output; third, fourth, fifth, and eleventh AND circuits respectively having first, second, third, and fourth inputs and an output; first and second monostable devices respectively having an input and an output; a bistable device having a SET input, a RESET input and an output; an OR circuit having first and second inputs and an output; said first input of said first AND circuit being connected to said first input terminal of said Decode circuit, a first INVERTER circuit connected between said second input terminal of said Decode circuit and said second input of said first AND circuit, and said output of said first AND circuit being connected to said first input of said third AND circuit, said fourth input of said fourth AND circuit, said first input of said fifth AND circuit, and said second input of said eleventh AND circuit; said first input of said second AND circuit being connected to said first input terminal of said Decode circuit, said second input of said second AND circuit being connected to said second input terminal of said Decode circuit, said output of said second AND circuit being connected to said first input of said sixth AND circuit, said first input of said seventh AND circuit, said first input of said eighth AND circuit, and said third input of said tenth AND circuit, and being adapted to provide said TEST MODE command; a second INVERTER circuit connected between said first input terminal of said Decode circuit and said second input of said ninth AND circuit; a third INVERTER circuit connected between said third input terminal of said Decode circuit and said third input of said first AND circuit, said third input of said fifth AND circuit, and said third input of said eighth AND circuit; a fourth INVERTER circuit connected between said fourth input terminal of said Decode circuit and said fourth input of said first AND circuit, said third input of said second AND circuit, and said third input of said seventh AND circuit; said second input of said third AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said third AND circuit being adapted to provide said SET NUMBER of SERIAL TESTS command; said first input of said fourth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said fourth AND circuit being connected to said third input terminal of said Decode circuit, and said output of said fourth AND circuit being adapted to provide said SET DISCONNECT command; said second input of said fifth AND circuit being connected to said fifth input terminal of said Decode circuit, said fourth input of said fifth AND circuit being connected to said fourth input terminal of said Decode circuit, and said output of said fifth AND circuit being adapted to provide a SET PIN SERIAL command; said second input of said sixth AND circuit being connected to said third input terminal of said Decode circuit, said third input of said sixth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said sixth AND circuit being adapted to provide said TEST PARALLEL command; said second input of said seventh AND circuit being connected to said third input terminal of said Decode circuit, said output of said seventh AND circuit being connected to said second input of said twelfth AND circuit and said input of Said second monostable device, and said output of said seventh AND circuit being adapted to provide said TEST SERIAL command; a fifthe INVERTER circuit connected to said output of said seventh AND circuit and said second input of said OR circuit; said set input of said bistable device being connected to said output of said second monostable device, said output of said second monostable device being adapted to provide said Z pulses, said reset input of said bistable device being connected to said output of said first monostable device; said first input of said tenth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said tenth AND circuit being connected to said output of said bistable device, said output of said bistable device being adapted to provide said STOP RAM command, and said output of said tenth AND circuit being adapted to provide said Y1 Time pulses; said input of said first monostable device being adapted to receive said STOP SERIAL TEST command; said second input of said eighth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said eighth AND circuit being adapted to provide said TEST TESTER command, said first input of said ninth AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said ninth AND circuit being adapted to provide said SET-UP MODE command; said first, third and fourth inputs of said eleventh AND circuit being respectively connected to said fifth, third and fourth input terminals of said Decode circuit, said output of said eleventh AND circuit being adapted to provide said SET CLOCK 1 command; a sixth INVERTER circuit having an input and an output and coupling said output of said first monostable device to said second input of said twelfth AND circuit, said output of said sixth INVERTER circuit being adapted to provide said Z pulses and said ouput of said twelfth AND circuit being adapted to provide a time delayed TEST SERIAL command; and said first input of said OR circuit being connected to said output of said first monostable device, said output of said OR circuit being adapted to provide a time-delayed NOT TEST SERIAL command; whereby a test system employing said Decode circuit will execute upon command a SET SERIAL NUMBER of TESTS operation, a TEST SERIAL operation, a SET DISCONNECT operation, a SET PIN SERIAL operation, a TEST PARALLEL operation, or a TEST TESTER operation.

Claim 60

A Decode circuit for use in a high speed electronic test system for testing high density circuit devices said tester performing a number of operations respectively initiated by operational code specifying bits, said Decode circuit being adapted to receive and respond to four operational codes specifying bits, Y-Time pulses and a STOP SERIAL TEST command in the form of an electrical manifestation, said Decode circuit being adapted to provide a plurality of commands respectively in the form of electrical manifestations, said plurality of electrical manifestations including the following SET NUMBER SERIAL TESTS command, TEST SERIAL command, NOT TEST SERIAL command, TEST MODE command, SET DISCONNECT command, SET PIN SERIAL command, TEST PARALLEL command, TEST TESTER command, a SET-UP MODE command, a SET CLOCK 1 command, a STOP RAM command, Y1-TIME pulses, Z pulses and z pulses, said Decode circuit being operative during each test cycle of a test operations including a sizeable number of test cycles, where each test cycle of said test system is controlleD, at least in part, by one or more of said electrical commands, said Decode circuit comprising; first, second, third and fourth input terminals for respectively receiving said first, second, third and fourth operational code specifying bits, and a fifth input terminal for receiving said Y-TIME pulses; first, second, ninth, ninth and twelfth AND circuits respectively having first and second inputs and an output; sixth, seventh, eighth and tenth AND circuits respectively having first, second and third inputs and an output; third, fourth, fifth, and eleventh AND circuits respectively having first, second, third, and fourth inputs and an output; first and second monostable devices respectively having an input and an output; a bistable device having a SET input, a RESET input and an output; an OR circuit having first and second inputs and an output; said first input of said first AND circuit being connected to said first input terminal of said Decode circuit, a first INVERTER circuit connected between said second input terminal of said Decode circuit and said second input of said first AND circuit, and said output of said first AND circuit being connected to said first input of said third AND circuit, said fourth input of said fourth AND circuit, said first input of said fifth AND circuit, and said second input of said eleventh AND circuit; said first input of said second AND circuit being connected to said first input terminal of said Decode circuit, said second input of said second AND circuit being connected to said second input terminal of said Decode circuit, said output of said second AND circuit being connected to said first input of said sixth AND circuit, said first input of said seventh AND circuit, said first input of said eighth AND circuit, and said third input of said tenth AND circuit, and being adapted to provide said TEST MODE command; a second INVERTER circuit connected between said first input terminal of said Decode circuit and said second input of said ninth AND circuit; a third INVERTER circuit connected between said third input terminal of said Decode circuit and said third input of said first AND circuit, said third input of said fifth AND circuit, and said third input of said eighth AND circuit; a fourth INVERTER circuit connected between said fourth input terminal of said Decode circuit and said fourth input of said first AND circuit, said third input of said second AND circuit, and said third input of said seventh AND circuit; said second input of said third AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said third AND circuit being adapted to provide said SET NUMBER of SERIAL TESTS command; said first input of said fourth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said fourth AND circuit being connected to said third input terminal of said Decode circuit, and said output of said fourth AND circuit being adapted to provide said SET DISCONNECT command; said second input of said fifth AND circuit being connected to said fifth input terminal of said Decode circuit, said fourth input of said fifth AND circuit being connected to said fourth input terminal of said Decode circuit, and said output of said fifth AND circuit being adapted to provide a SET PIN SERIAL command; said second input of said sixth AND circuit being connected to said third input terminal of said Decode circuit, said third input of said sixth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said sixth AND circuit being adapted to provide said TEST PARALLEL command; said second input of said seventh AND circuit being connected to said third input terminal of said Decode circuit, said output of said seventh AND circuit being connected to said second input of said twelfth AND circuit and said input of Said second monostable device, and said output of said seventh AND circuit being adapted to provide said TEST SERIAL command; a fifthe INVERTER circuit connected to said output of said seventh AND circuit and said second input of said OR circuit; said set input of said bistable device being connected to said output of said second monostable device, said output of said second monostable device being adapted to provide said Z pulses, said reset input of said bistable device being connected to said output of said first monostable device; said first input of said tenth AND circuit being connected to said fifth input terminal of said Decode circuit, said second input of said tenth AND circuit being connected to said output of said bistable device, said output of said bistable device being adapted to provide said STOP RAM command, and said output of said tenth AND circuit being adapted to provide said Y1 Time pulses; said input of said first monostable device being adapted to receive said STOP SERIAL TEST command; said second input of said eighth AND circuit being connected to said fourth input terminal of said Decode circuit, said output of said eighth AND circuit being adapted to provide said TEST TESTER command, said first input of said ninth AND circuit being connected to said fifth input terminal of said Decode circuit, said output of said ninth AND circuit being adapted to provide said SET-UP MODE command; said first, third and fourth inputs of said eleventh AND circuit being respectively connected to said fifth, third and fourth input terminals of said Decode circuit, said output of said eleventh AND circuit being adapted to provide said SET CLOCK 1 command; a sixth INVERTER circuit having an input and an output and coupling said output of said first monostable device to said second input of said twelfth AND circuit, said output of said sixth INVERTER circuit being adapted to provide said Z pulses and said ouput of said twelfth AND circuit being adapted to provide a time delayed TEST SERIAL command; and said first input of said OR circuit being connected to said output of said first monostable device, said output of said OR circuit being adapted to provide a time-delayed NOT TEST SERIAL command; whereby a test system employing said Decode circuit will execute upon command a SET SERIAL NUMBER of TESTS operation, a TEST SERIAL operation, a SET DISCONNECT operation, a SET PIN SERIAL operation, a TEST PARALLEL operation, or a TEST TESTER operation.

Claim 61

In a high speed electronic test system, for testing high circuit density devices fabricated by large scale integration techniques, said test system employing a pattern of parallel test data and a pattern of serial test data and where said serial test data bears a known fixed relationship to said parallel test data, said test system being responsive to a controller and including test data processing means, said test data processing means comprising: storage means for storing said parallel test data pattern and a selected portion of said serial test data pattern, said portion of said serial test data pattern being stored in a format in accordance with said known fixed relationship of said serial test data to said parallel test data; and, circuit means, responsive to said controller and cooperating with said storage means for on as called for basis by the controller constructing from said parallel test data pattern and said selected portion of said serial test data pettern, a complete serial test pattern, whereby the storage capacity required to store mixed parallel serial test data is minimized.

Claim 62

In a high speed electronic test system, for testing high circuit density devices fabricated by large scale integration techniques, said test system employing a pattern of parallel test data and a pattern of serial test data and where said serial test data bears a known fixed relationship to said parallel test data, said test system being responsive to a controller and including test data processing means, said test data processing means comprising: storage means for storing said parallel test data pattern and a selected portion of said serial test data pattern, said portion of said serial test data pattern being stored in a format in accordance with said known fixed relationship of said serial test data to said parallel test data; and, circuit means, responsive to said controller and cooperating with said storage means for on as called for basis by the controller constructing from said parallel test data pattern and said selected portion of said serial test data pettern, a complete serial test pattern, whereby the storage capacity required to store mixed parallel serial test data is minimized.