US5003487A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
Assignee: International Business Machines Corp
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Filing: 1988-06-28
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Granted: 1991-03-26
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Expires: 2008-06-28
Abstract
Abstract A computer program is disclosed providing a sequence of automated logic synthesis routines having three phases. Phase I identifies an estimated critical path by assuming optimum allocation within a "best-fit" preliminary assignment of the technology to a technology-independent model, and optimizes the estimated model for speed. Phase II provides a technology-legal model, and ends by calculating the actual timing provided by the technology-legal model. Phase III uses self-limiting routines, and routines that are unlikely to produce technology violations, to fine tune the production and performance characteristics of the legal model.
Inventors
- 👤 Anthony D. Drumm
- 👤 Randall C. Itskin
- 👤 Kenneth W. Todd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:53
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312; G06F30/327; G06F2119/00; G06F2119/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A method of logic synthesis that avoids producing the uncorrectable timing problems that are encountered when rules for a given technology are assigned to a technology independent logic model, said given technology having a prescribed set of available functional logic blocks, said method comprising the steps of: (a) identifying logic blocks in the model that are not available in said given technology; (b) estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model; (c) calculating the timing values for the preliminary model using fan-out values that are limited to a predetermined maximum load; (d) applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and (e) correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.
Claim 2
Independent Claim
153 words
A method of logic synthesis that avoids producing the uncorrectable timing problems that are encountered when rules for a given technology are assigned to a technology independent logic model, said given technology having a prescribed set of available functional logic blocks, said method comprising the steps of: (a) identifying logic blocks in the model that are not available in said given technology; (b) estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model; (c) calculating the timing values for the preliminary model using fan-out values that are limited to a predetermined maximum load; (d) applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and (e) correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.
Claim 3
Dependent Claim
21 words
The method of claim 1 further comprising the step of locally recalculating slacks in the model after a correction is made.
Claim 4
Dependent Claim
27 words
The method of claim 1 further comprising the step of providing adjusted average delay times for selected blocks in the model for use in timing value calculations.
Claim 5
Dependent Claim
30 words
The method of claim 1 further comprising the step of forcing a timing correction routine to ignore selected eligible blocks in the model when making timing corrections in the model.
Claim 6
Dependent Claim
154 words
Apparatus for producing logic synthesis by assigning rules for a given technology to a technology-independent logic model while avoiding uncorrectable timing problems, said given technology having a prescribed set of available functional logic blocks, said apparatus comprising: (a) means for identifying logic blocks in the model that are not available in said given technology; (b) means for estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model; (c) means for calculating the timing values for the preliminary model using fan-out load values that are limited to a predetermined maximum load; (d) means for applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and (e) means for correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.
Claim 7
Dependent Claim
154 words
Apparatus for producing logic synthesis by assigning rules for a given technology to a technology-independent logic model while avoiding uncorrectable timing problems, said given technology having a prescribed set of available functional logic blocks, said apparatus comprising: (a) means for identifying logic blocks in the model that are not available in said given technology; (b) means for estimating the timing characteristics of said logic blocks that are not available in said given technology based upon the characteristics of similar logic blocks that are available, thereby providing a preliminary model; (c) means for calculating the timing values for the preliminary model using fan-out load values that are limited to a predetermined maximum load; (d) means for applying timing correction routines to the critical path in the preliminary model, thereby providing an estimated model; and (e) means for correcting violations of the rules of said given technology in the estimated model, thereby providing a technology-legal model.
Claim 8
Dependent Claim
20 words
The apparatus of claim 5 further comprising means for locally recalculating slacks in the model after a correction is made.
Claim 9
Dependent Claim
26 words
The apparatus of claim 5 further comprising means for providing adjusted average delay times for selected blocks in the model for use in timing value calculations.
Claim 10
Dependent Claim
29 words
The apparatus of claim 5 further comprising means for forcing a timing correction routine to ignore selected eligible blocks in the model when making timing corrections in the model.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |