Transistor sizing system for integrated circuits

Claim 1

An integrated circuit comprising memory elements, input ports, output ports and a plurality of active elements constructed in accordance with a layout arrangement where at least one of said output ports is a critical output port that develops output signals with a delay that essentially is at a preselected maximum level, where each of said critical output ports has an associated critical path that contains those of said active elements whose size variations affect the signal delay of said critical output, and wherein at least some of said active elements in said critical paths are at sizes greater than a minimum size, said active element sizes being selected such that reducing the size of any active element in said critical paths causes the signal delay of at least one of said critical output ports to exceed said preselected maximum delay.

Claim 3

A method for altering a given layout of an integrated circuit comprising the steps of: designating said given layout as the current layout; performing a timing analysis of said current layout to identify and output port of said integrated circuit that has a slower response than all other output ports of said integrated circuit; performing a sensitivity analysis on the identified output port to locate an active element of said integrated circuit whose change in size improves the speed of response of said identified output port by the greatest amount; automatically altering the size of said located active element; and designating the layout resulting from said altering as the current layout and reiterating through the steps of this method until preselected criteria are met.

Claim 4

A method for altering a given layout of an integrated circuit comprising the steps of: designating said given layout as the current layout; performing a timing analysis of said current layout to identify and output port of said integrated circuit that has a slower response than all other output ports of said integrated circuit; performing a sensitivity analysis on the identified output port to locate an active element of said integrated circuit whose change in size improves the speed of response of said identified output port by the greatest amount; automatically altering the size of said located active element; and designating the layout resulting from said altering as the current layout and reiterating through the steps of this method until preselected criteria are met.

Claim 11

A method for improving the layout design of an electronic circuit having input ports, output ports, and active elements therebetween, with respect fo specified criteria, comprising the steps of: representing said active elements by a model characterized by a function that is convex in the neighborhood of the operating point of said active elements; obtaining information of the output signal timing delay between all of said input ports and each of said output ports; selecting an output port from said output ports that, in accordance with said step of obtaining information, develops an output signal that is delayed more than all other output signals of said output ports; investigating a subset of said active elements to determine the effect of altering the size of an active element in said subset on the delay of the output signal of said selected output port; modifying that active element which, in accordance with said step of investigating, is determined to have the greatest effect on improving said delay of the output signal of said selected output port; and returning to said step of obtaining information unless said specified criteria are met.

Claim 12

A method for improving the layout design of an electronic circuit having input ports, output ports, and active elements therebetween, with respect fo specified criteria, comprising the steps of: representing said active elements by a model characterized by a function that is convex in the neighborhood of the operating point of said active elements; obtaining information of the output signal timing delay between all of said input ports and each of said output ports; selecting an output port from said output ports that, in accordance with said step of obtaining information, develops an output signal that is delayed more than all other output signals of said output ports; investigating a subset of said active elements to determine the effect of altering the size of an active element in said subset on the delay of the output signal of said selected output port; modifying that active element which, in accordance with said step of investigating, is determined to have the greatest effect on improving said delay of the output signal of said selected output port; and returning to said step of obtaining information unless said specified criteria are met.

Claim 24

A system for altering the layout of at least a portion of an integrated circuit comprising: first means, responsive to an applied design specification and to an activation signal from a sixth means, for developing information concerning relative time delays of output signals of said integrated circuit; second means, responsive to said first means, for selecting an output of said integrated circuit that develops an output signal more slowly than other outputs of said integrated circuit; third, responsive to said second means, means for identifying active elements of said integrated circuit whose size alterations affect the output signal delay of said selected output; fourth means, responsive to said third means, for selecting an active element from among the ones singled out by said third means, said active element offering the largest improvement in speed of the signals of said selected output in response to an alteration in the size of said active element, and accordingly modifying the size of that active element; fifth means, responsive to said fourth means, for updating said information concerning relative time delays, based on the size modifications called for by said fourth means; and sixth means for passing an activation signal to said first means as long as specified criteria are not met.

Claim 25

A system for altering the layout of at least a portion of an integrated circuit comprising: first means, responsive to an applied design specification and to an activation signal from a sixth means, for developing information concerning relative time delays of output signals of said integrated circuit; second means, responsive to said first means, for selecting an output of said integrated circuit that develops an output signal more slowly than other outputs of said integrated circuit; third, responsive to said second means, means for identifying active elements of said integrated circuit whose size alterations affect the output signal delay of said selected output; fourth means, responsive to said third means, for selecting an active element from among the ones singled out by said third means, said active element offering the largest improvement in speed of the signals of said selected output in response to an alteration in the size of said active element, and accordingly modifying the size of that active element; fifth means, responsive to said fourth means, for updating said information concerning relative time delays, based on the size modifications called for by said fourth means; and sixth means for passing an activation signal to said first means as long as specified criteria are not met.