Configurable logic gate array

Abstract

Abstract A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing "high" and "low" logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals. With such arrangement, there is a reduction in the test program development time since bringing the output to the desired state (high or low) be sequencing through function testing to achieve the desired state on the desired pin (an error prone, time consuming process requiring full understanding of the logic implemented and rationale applied by customer in generating test vectors) is eliminated. Further, with such an arrangement, parametric testing of the output signals by the gates in the array is performed by merely driving each output buffer circuit to "high" or "low" logic states thereby reducing parametric testing time of the gate array after the logic gates have been selectively electrically interconnected to provide the desired predetermined logic function.

Inventors

• 👤 Deepak Mehrotra
• 👤 Rajni Kant
• 👤 Kishor M. Patel

Bibliographic Details