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US5960191A
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Emulation system with time-multiplexed interconnect
Assignee: Cadence Design Systems Inc
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Filing: 1997-05-30
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Granted: 1999-09-28
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Expires: 2017-05-30
Abstract
Abstract A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
Inventors
- 👤 Stephen P. Sample
- 👤 Mikhail Bershteyn
- 👤 Michael R. Butts
- 👤 Jerry R. Bauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2853; G01R31/317; G01R31/31712; G01R31/31717; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; Y; Y10; Y10S; Y10S370/00; Y10S370/916
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
319 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and a set of fixed electrical conductors of said printed circuit board connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 2
Dependent Claim
319 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and a set of fixed electrical conductors of said printed circuit board connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 3
Dependent Claim
19 words
An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable logic devices comprise programmable gate arrays.
Claim 4
Dependent Claim
20 words
An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable logic devices comprise field programmable gate arrays.
Claim 5
Dependent Claim
19 words
An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise programmable gate arrays.
Claim 6
Dependent Claim
20 words
An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise field programmable gate arrays.
Claim 7
Dependent Claim
27 words
An electrically reconfigurable logic assembly as recited in claim 1, wherein said reprogrammable interconnect devices comprise an integrated circuit having an array of crosspoint switches fabricated thereon.
Claim 8
Dependent Claim
446 words
A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals.
Claim 9
Dependent Claim
446 words
A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals.
Claim 10
Dependent Claim
20 words
The reprogrammable logic emulation system of claim 7 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.
Claim 11
Dependent Claim
57 words
The reprogrammable logic emulation system of claim 7 wherein said plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips and said plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips are implemented using said logic blocks and said input/output blocks of said plurality of reprogrammable logic chips.
Claim 12
Dependent Claim
21 words
The reprogrammable logic emulation system of claim 7 wherein each of said time-multiplexed signals is a combination of two design signals.
Claim 13
Dependent Claim
21 words
The reprogrammable logic emulation system of claim 7 wherein each of said time-multiplexed signals is a combination of four design signals.
Claim 14
Dependent Claim
462 words
A reprogrammable logic emulation system for implementing an integrated circuit design, the integrated circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions, said logical functions including both combinational logic functions and sequential logic functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more signals from said data path structure of said integrated circuit design into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signal and dividing said second time-multiplexed signals into one or more internal signals.
Claim 15
Dependent Claim
462 words
A reprogrammable logic emulation system for implementing an integrated circuit design, the integrated circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions, said logical functions including both combinational logic functions and sequential logic functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more signals from said data path structure of said integrated circuit design into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; and said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signal and dividing said second time-multiplexed signals into one or more internal signals.
Claim 16
Dependent Claim
20 words
The reprogrammable logic emulation system of claim 12 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.
Claim 17
Dependent Claim
51 words
The reprogrammable logic emulation system of claim 12 wherein said plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips and said plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips implemented using programmable resources of said plurality of reprogrammable logic chips.
Claim 18
Dependent Claim
21 words
The reprogrammable logic emulation system of claim 12 wherein each of said time-multiplexed signals is a combination of two design signals.
Claim 19
Dependent Claim
21 words
The reprogrammable logic emulation system of claim 12 wherein each of said time-multiplexed signals is a combination of four design signals.
Claim 20
Dependent Claim
284 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said input/output terminals on each of said plurality of reprogrammable interconnect devices receiving a time-multiplexed input and placing said time-multiplexed input on a different one of said input/output terminals; and a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 21
Dependent Claim
284 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said input/output terminals on each of said plurality of reprogrammable interconnect devices receiving a time-multiplexed input and placing said time-multiplexed input on a different one of said input/output terminals; and a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 22
Dependent Claim
19 words
An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable logic devices comprise programmable gate arrays.
Claim 23
Dependent Claim
20 words
An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable logic devices comprise field programmable gate arrays.
Claim 24
Dependent Claim
19 words
An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise programmable gate arrays.
Claim 25
Dependent Claim
20 words
An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise field programmable gate arrays.
Claim 26
Dependent Claim
27 words
An electrically reconfigurable logic assembly as recited in claim 17, wherein said reprogrammable interconnect devices comprise an integrated circuit having an array of crosspoint switches fabricated thereon.
Claim 27
Dependent Claim
464 words
A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals; and each of said first time-multiplexed signals and said second time-multiplexed signals are a combination of four design signals.
Claim 28
Dependent Claim
464 words
A reprogrammable logic emulation system for implementing a circuit design, the circuit design characterized by a clock path structure and a data path structure, comprising: a plurality of reprogrammable logic chips disposed on a first circuit board, each of said first plurality of logic chips comprising logic blocks for implementing logical functions and input/output blocks for implementing input/output functions, each of said first plurality of logic chips further comprising a plurality of input/output pins which are programmably electrically connectable to said logic blocks; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of output multiplexers implemented in each of said plurality of reprogrammable logic chips, each of said plurality of output multiplexers electrically communicating with one of said input/output pins on said reprogrammable logic chips; a plurality of reprogrammable interconnect chips disposed on said first circuit board, each of said reprogrammable interconnect chips having input/output pins and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output pins; a plurality of output multiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said output multiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable interconnect chips; a plurality of input demultiplexers implemented in each of said plurality of reprogrammable interconnect chips, each of said plurality of input demultiplexers electrically communicating with one of said input/output pins on said plurality of reprogrammable logic chips; a plurality of conductive traces disposed in said first circuit board, each of said plurality of conductive traces electrically connecting one of said input/output pins on one of said reprogrammable logic chips to one of said input/output pins on one of said reprogrammable interconnect chips such that each of said reprogrammable interconnect chips is connected to at least one but not all of said programmable input/output pins on each of said reprogrammable logic chips; said plurality of output multiplexers implemented in said plurality of reprogrammable logic chips combining one or more internal signals into first time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable interconnect chips receiving said first time-multiplexed signals and dividing said first time-multiplexed signals into one or more component signals; said plurality of output multiplexers implemented in said plurality of reprogrammable interconnect chips combining said one or more component signals into second time-multiplexed signals; said plurality of input demultiplexers implemented in said plurality of reprogrammable logic chips receiving said second time-multiplexed signals and dividing said second time-multiplexed signals into one or more internal signals; and each of said first time-multiplexed signals and said second time-multiplexed signals are a combination of four design signals.
Claim 29
Dependent Claim
366 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to a clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit boards, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to said clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 30
Dependent Claim
366 words
An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to a clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices disposed on said printed circuit boards, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer having a select input electrically connected to said clock signal, said output multiplexer having a select input electrically connected to said clock signal, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
Claim 31
Dependent Claim
16 words
The electrically reconfigurable logic assembly of claim 24 wherein said clock signal is a synchronous signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-27 | 2003-03-29 | 2003-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-27 | 2007-03-29 | 2007-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-27 | 2011-03-29 | 2011-09-28 | $7700.00 | Window Closed / Lapsed |