EP0217291A2
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EP
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Circuit translator
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1986-09-25
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Granted: —
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Expires: 2006-09-25
Abstract
Abstract In order to translate an original circuit (21) consisting of a set of first devices into a target circuit - (22) which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, in a circuit translator are provided memory means for storing translation rules (210, 220) in the first devices, translation rules (240, 250) in the second devices, and translation rules (230) between the first devices and the second devices, and translation means (20; 110, 120, 130) which successively refers to these translation rules and translates the original circuit data (21) into the target circuit data (22) via steps that translate the original circuit data (21) into a plurality of intermediate data (30, 31).
Inventors
- 👤 Tamotsu Nishiyama
- 👤 Toshinori Watanabe
- 👤 Noboru Horie
- 👤 Makoto Furihata
- 👤 Yasuo Kominami
- 👤 Fumihiko Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 07:04
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; Y; Y10; Y10S; Y10S706/00; Y10S706/902; Y10S706/919; Y10S706/921
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
A circuit translator for translating an original circuit constituted by a set of first elements (21) into a logically equivalent target circuit constituted by a set of second elements (22), characterised by first memory means (210, 220) which stores translation rules in the set of said first elements (21); second memory means (240, 250) which stores translation rules in the set of said second elements (22): third memory means (230) which stores translation rules from the set of said first elements (21) into the set of said second elements (22); and translation means (20; 110, 120, 130) which permits translation rules automatically selected from said first memory means (210, 220) to act upon the original circuit data (21) to translate the data into first intermediate data (30), which permits translation rules automatically selected from said third memory means (23) to act upon said first intermediate data (30) to translate the data into second intermediate data (31), and which permits translation rules automatically selected from said second memory means (240, 250) to act upon said second intermediate data (31) to translate the data into target circuit data (22).
Claim 2
Dependent Claim
187 words
A circuit translator for translating an original circuit constituted by a set of first elements (21) into a logically equivalent target circuit constituted by a set of second elements (22), characterised by first memory means (210, 220) which stores translation rules in the set of said first elements (21); second memory means (240, 250) which stores translation rules in the set of said second elements (22): third memory means (230) which stores translation rules from the set of said first elements (21) into the set of said second elements (22); and translation means (20; 110, 120, 130) which permits translation rules automatically selected from said first memory means (210, 220) to act upon the original circuit data (21) to translate the data into first intermediate data (30), which permits translation rules automatically selected from said third memory means (23) to act upon said first intermediate data (30) to translate the data into second intermediate data (31), and which permits translation rules automatically selected from said second memory means (240, 250) to act upon said second intermediate data (31) to translate the data into target circuit data (22).
Claim 3
Dependent Claim
112 words
A circuit translator according to claim 1, wherein the translation rules stored in said first memory means (210, 220) are constituted by connecting relation extracting rules (210) that are necessary for preparing decision data to decide a connecting relation among the elements of the original circuit and a function produced by the elements in the original circuit, and basic concept extracting rules (220) for extracting basic concepts in the original circuit system, and wherein said translation means (20; 110) selects said connecting relation extracting rules (210) and said basic concept extracting rules (22), and permits them to act upon the original circuit data (21) to translate them into first intermediate data (30).
Claim 4
Dependent Claim
45 words
A circuit translator according to claim 1 or 2, wherein translation rules stored in said third memory means (230) are constituted by basic concept translating rules that translate basic elements of translation in the original circuit system into basic elements in the target circuit system.
Claim 5
Dependent Claim
106 words
A circuit translator according to any of claims 1 to 3, wherein the translation rules stored in said second memory means (240, 250) are constituted by target circuit generating rules (240) and circuit optimizing rules (250) in the target circuit system, and said translation means (20; 130) selects said target circuit generating rules (240) and permits them to act upon said second intermediate data (31) to form from the second intermediate data the target circuit data logically equivalent to the original circuit, and further selects said circuit optimizing rules (250), and permits them to act upon said target circuit data (22) to optimize the target circuit
Claim 6
Dependent Claim
61 words
A circuit translator according to any of claims 2 to 4, wherein said first memory means - (210, 220) includes means that holds said decision data, and said translation means (20; 110) generates the first intermediate data (30) from the original circuit data (21) using said decision data, and generates the target circuit data (22) from the second intermediate data (31).
Claim 7
Dependent Claim
70 words
A circuit translator according to any of claims 2 to 4, wherein said translation means (20) provides priority for said basic concept extracting rules (220), said basic concept translating rules (230), said target circuit generating rules (240), and said target circuit optimizing rules (250), and successively selects the rules in the order of decreasing priority until suitable rules are found, and permits the rules to act upon the corresponding data.
References Cited (Backward Citations)
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