US5950304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods of making semiconductor chip assemblies
Assignee: Adeia Semiconductor Solutions LLC
•
Filing: 1997-05-21
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Granted: 1999-09-14
•
Expires: 2017-05-21
Abstract
Abstract A semiconductor chip having contacts on the central region of its top surface is provided with a dielectric element overlying the central portion of the top surface. The dielectric element has a first surface facing toward the chip and a second surface facing away from the chip, a hole encompassing the central contacts and an edge bounding the hole. Central contact leads extend from the central contacts on the chip to central terminals on the dielectric element. The terminals on the dielectric element may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the dielectric element, are flexible so that the terminals are moveable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The dielectric element may be provided with a compliant layer disposed between the terminals and the chip. The entire assembly is compact.
Inventors
- 👤 Igor Y. Khandros
- 👤 Thomas H. DiStefano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:20
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7402; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10P74/00; H10P74/27; H10P74/273; H10W; H10W70/00; H10W70/40; H10W70/479; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/65; H10W70/657; H10W70/67; H10W70/68; H10W70/688; H10W74/00; H10W74/10; H10W74/111; H10W74/131; H10W74/144; H10W90/00; H10P72/7416; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/50; H10W72/541; H10W72/547; H10W72/5473; H10W72/60; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/941; H10W72/9413; H10W90/20; H10W90/284; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/4913; Y10T29/49144; Y10T29/49146; Y10T29/49147; Y10T29/49169; Y10T29/49171
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
154 words
A method of making a semiconductor chip assembly comprising the steps of: (a) providing a semiconductor chip having a front surface defining the top of the chip, said front surface including a central region and a peripheral region surrounding said central region, whereby said central region is disposed inwardly of said peripheral region, said chip having central contacts disposed in said central region of said front surface; (b) assembling a dielectric element to said chip so that said dielectric element overlies said chip front surface, said dielectric element having a first surface facing towards said chip and a second surface facing away from said chip, a plurality of terminals disposed on said dielectric element and a hole encompassing said central contacts with an edge bounding said hole; (c) connecting a plurality of central contact leads between at least some of said central contacts and at least some of said terminals on said dielectric element.
Claim 2
Independent Claim
154 words
A method of making a semiconductor chip assembly comprising the steps of: (a) providing a semiconductor chip having a front surface defining the top of the chip, said front surface including a central region and a peripheral region surrounding said central region, whereby said central region is disposed inwardly of said peripheral region, said chip having central contacts disposed in said central region of said front surface; (b) assembling a dielectric element to said chip so that said dielectric element overlies said chip front surface, said dielectric element having a first surface facing towards said chip and a second surface facing away from said chip, a plurality of terminals disposed on said dielectric element and a hole encompassing said central contacts with an edge bounding said hole; (c) connecting a plurality of central contact leads between at least some of said central contacts and at least some of said terminals on said dielectric element.
Claim 3
Dependent Claim
28 words
A method as claimed in claim 1, wherein said terminals are moveable with respect to said central contacts so as to compensate for thermal expansion of said chip.
Claim 4
Dependent Claim
35 words
A method as claimed in claim 1, wherein each said central contact lead includes a terminal end integrally formed with one of said terminals and a contact end extending to one of said central contacts.
Claim 5
Dependent Claim
14 words
A method as claimed in claim 3, wherein said central contact leads are flexible.
Claim 6
Dependent Claim
28 words
A method as claimed in claim 1, wherein said dielectric element includes a compliant layer of a low modulus material, said compliant layer being disposed beneath said terminals.
Claim 7
Dependent Claim
45 words
A method as claimed in claim 5, wherein said dielectric element further includes a thin, flexible top layer formed from a material selected from the group consisting of thermoset and thermoplastic polymers overlying said compliant layer and defining said second surface of said dielectric element.
Claim 8
Dependent Claim
22 words
A method as claimed in claim 1, wherein some of said plurality of terminals are disposed adjacent the edge bounding said hole.
Claim 9
Dependent Claim
22 words
A method as claimed in claim 1, wherein said plurality of terminals are disposed at said second surface of said dielectric element.
References Cited (Backward Citations)
US3302067A
Cited
US35119A
Cited
US3614832A
Cited
US3390308A
Cited
US3426252A
Cited
US3487541A
Cited
US3474297A
Cited
US3689991A
Cited
US3680206A
Cited
US3795037A
Cited
US3683105A
Cited
US3680037A
Cited
US3864728A
Cited
US3724068A
Cited
US3772575A
Cited
US3832769A
Cited
US3611061A
Cited
US3862790A
Cited
US3825353A
Cited
US3823467A
Cited
US3952404A
Cited
US3868724A
Cited
UST955008I4
Cited
US4189825A
Cited
US4356374A
Cited
US4237607A
Cited
FR2405839A1
Cited
US4179802A
Cited
SU1003396A1
Cited
US4349862A
Cited
FR2495839B1
Cited
US4410905A
Cited
US4437141A
Cited
US4536469A
Cited
US4658332A
Cited
US4648179A
Cited
US4545610A
Cited
US4751199A
Cited
US4751482A
Cited
US4670770A
Cited
US4574470A
Cited
US4597617A
Cited
US4627151A
Cited
US4685998A
Cited
US4667220A
Cited
US4772936A
Cited
US4655524A
Cited
US4649415A
Cited
US4604644A
Cited
US4628406A
Cited
FR2586885B1
Cited
US4710798A
Cited
US4874721A
Cited
US4924353A
Cited
US4700473A
Cited
US4709468A
Cited
US4721993A
Cited
US4890157A
Cited
US4764804A
Cited
US4695870A
Cited
US4681654A
Cited
US4793814A
Cited
US4878098A
Cited
US4937203A
Cited
US4783695A
Cited
US4918811A
Cited
US4860088A
Cited
US4811082A
Cited
US4897534A
Cited
US5055913A
Cited
US4814295A
Cited
US4818728A
Cited
US5086337A
Cited
US4893172A
Cited
US4783719A
Cited
US4855867A
Cited
US4766670A
Cited
US4942140A
Cited
US4796078A
Cited
US4967261A
Cited
US4855872A
Cited
US4866841A
Cited
US4926241A
Cited
US4847146A
Cited
US4937707A
Cited
US4842662A
Cited
US4993954A
Cited
US4887148A
Cited
USRE35119E
Cited
US4937653A
Cited
US4975765A
Cited
US4884122A
Cited
US4941033A
Cited
US5192716A
Cited
US5055907A
Cited
US5023205A
Cited
US5027191A
Cited
US4954878A
Cited
US5504035A
Cited
US5053922A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |