US5055913A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Terminal arrangement for integrated circuit device
Assignee: GAO Gesellschaft fuer Automation und Organisation mbH
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Filing: 1989-10-26
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Granted: 1991-10-08
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Expires: 2009-10-26
Abstract
Abstract An integrated circuit includes electrically conductive terminals arranged to be connected to external leads for communication between the leads and the circuitry of the integrated circuit device. The terminals of the circuit device are disposed at a surface away from the perimeter of the integrated circuit device so that the terminals are arranged in a specified area that is small compared to the overall area of the integrated circuit device, preferably in the center of a surface of the integrated circuit device.
Inventors
- 👤 Yahya Haghiri-Tehrani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:54
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K19/077; G06K19/07745; G06K19/07747; G06K19/07718; G06K19/0772; G06K19/07728; G06K19/07743; H; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/08; H10W70/09
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
112 words
In an integrated circuit semiconductor chip device including integrated ccircuitry and electrically conductive terminals on the chip surface, said surface limited by chip edge boundaries, said terminals connected to said integrated circuitry and adapted to be connected to external leads for communication between the external leads and the integrated circuitry, the improvement comprising: said terminals being disposed as a group array located over a predetermined area of the chip surface spaced inwardly from the chip edge boundaries, said area terminating at area boundaries, at least one area boundary and the geometric center of said area being closer to the center of the chip surface than the closest directly opposite chip edge boundary.
Claim 2
Dependent Claim
112 words
In an integrated circuit semiconductor chip device including integrated ccircuitry and electrically conductive terminals on the chip surface, said surface limited by chip edge boundaries, said terminals connected to said integrated circuitry and adapted to be connected to external leads for communication between the external leads and the integrated circuitry, the improvement comprising: said terminals being disposed as a group array located over a predetermined area of the chip surface spaced inwardly from the chip edge boundaries, said area terminating at area boundaries, at least one area boundary and the geometric center of said area being closer to the center of the chip surface than the closest directly opposite chip edge boundary.
Claim 3
Dependent Claim
43 words
The improvement in an integrated circuit device as claimed in claim 1, wherein said chip surface includes at least one central zone equidistant from at least one pair of opposite edge boundaries and said array of terminals is disposed in said central zone.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |